#ifndef HI1823_CSR_SM_TYPEDEF_H
#define HI1823_CSR_SM_TYPEDEF_H

#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* * __cplusplus */

/* **
 * Union name :    SMRT_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmrtVersion {
    struct tagStSmrtVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smrtVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smrtVersion : 32; /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMRT_VERSION_U;

/* **
 * Union name :    SMXR_CFG1
 * @brief               SMXR cofigure registers
 * Description:
 */
typedef union tagUnSmxrCfg1 {
    struct tagStSmxrCfg1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int rpUncrtErrInjReq : 1; /* * [31:31]ECC uncrt err injection requestion;err injection start when
                                        posedge of this bit is detected; After Err injection start, err is injected when
                                        a memory read is is sued to the memory.Enable memory check, when use this err
                                        inection function. */
        unsigned int rpCrtErrInjReq : 1;   /* * [30:30]ECC crt err injection requestion;err injection start when posedge
                                        of this bit is detected; After Err injection start, err is injected when a memory
                                        read is issu ed to the memory.Enable memory check, when use this err inection
                                        function. */
        unsigned int rpSmUncrtErrMask : 7; /* * [29:23]Fatal Error Mask.For SMLbit[0]：smxt fatal error
                                        mask;bit[1]：smmc_l fatal error maskbit[2]：smeg_core fatal error
                                        maskbit[3~6]：Reserved.For SMFbit[0]：smxr fatal e rror mask;bit[1]：smxt fatal
                                        error mask;bit[2]：smmc_f fatal error maskbit[3]：smeg_core 3 fatal error
                                        maskbit[4]：smeg_core 2 fatal error maskbit[5]：smeg_core 1 fa tal error
                                        maskbit[6]：smeg_core 0 fatal error mask7 fatal error source for SMF and 3 fatal
                                        error source for SML, SW can mask the fatal error of each source respe
                                        ctively.1'b0: Mask the fatal error;1'b1: Unmask the fatal error */
        unsigned int rpSmUncrtErrClr : 1; /* * [22:22]Clr the Fatal error of SML/SMF.SW can write 0 then 1 to generate a
                                           * rising edge to clear the fatal error
                                           */
        unsigned int tifoePftchWqeNum : 2; /* * [21:20]TIFOE pre-fetch API pre-fetch WQE number */
        unsigned int tifoePftchCtl : 2;    /* * [19:18]TIFOE pre-fetch API control bit2:1;For details, please refer to
                                            * description of TIFOE prefetch API in Hi1822V100 FS SMF API.docx
                                            */
        unsigned int reserved0 : 1;        /* * [17:17]reserved */
        unsigned int memRet1n : 1;         /* * [16:16]control of memory pin RET1N */
        unsigned int tpRamTmod : 8;        /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                            * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                            */
        unsigned int iwarpPiCopyEnb : 1;   /* * [7:7]IWARP PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch
                                            * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid
                                            */
        unsigned int rocePiCopyEnb : 1;    /* * [6:6]ROCE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch
                                            * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid
                                            */
        unsigned int tifoePiCopyEnb : 1;   /* * [5:5]TIFOE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch
                                            * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid
                                            */
        unsigned int reserved1 : 2;        /* * [4:3]reserved */
        unsigned int smxrCntSel : 2; /* * [2:1]smxr cnt source select:2'b00: Count disable2'b01: Count number of API
                                  segment smxr received;2'b10: Count number of messages smxr received2'b11: Count number
                                  of flitssmxr received */
        unsigned int memChkEn : 1;   /* * [0:0]memory check enable.1'b0:disable all memories err check.1'b1:enable all
                                      * memories err check.
                                      */
#else
        unsigned int memChkEn : 1;     /* * [0:0]memory check enable.1'b0:disable all memories err check.1'b1:enable all
                                        * memories err check.
                                        */
        unsigned int smxrCntSel : 2;   /* * [2:1]smxr cnt source select:2'b00: Count disable2'b01: Count number of API
                                    segment smxr received;2'b10: Count number of messages smxr received2'b11: Count number
                                    of flitssmxr received */
        unsigned int reserved1 : 2;    /* * [4:3]reserved */
        unsigned int tifoePiCopyEnb : 1;   /* * [5:5]TIFOE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch
                                            * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid
                                            */
        unsigned int rocePiCopyEnb : 1;    /* * [6:6]ROCE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch
                                            * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid
                                            */
        unsigned int iwarpPiCopyEnb : 1;   /* * [7:7]IWARP PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch
                                            * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid
                                            */
        unsigned int tpRamTmod : 8;        /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                            * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                            */
        unsigned int memRet1n : 1;         /* * [16:16]control of memory pin RET1N */
        unsigned int reserved0 : 1;        /* * [17:17]reserved */
        unsigned int tifoePftchCtl : 2;    /* * [19:18]TIFOE pre-fetch API control bit2:1;For details, please refer to
                                            * description of TIFOE prefetch API in Hi1822V100 FS SMF API.docx
                                            */
        unsigned int tifoePftchWqeNum : 2; /* * [21:20]TIFOE pre-fetch API pre-fetch WQE number */
        unsigned int rpSmUncrtErrClr : 1; /* * [22:22]Clr the Fatal error of SML/SMF.SW can write 0 then 1 to generate a
                                           * rising edge to clear the fatal error
                                           */
        unsigned int rpSmUncrtErrMask : 7; /* * [29:23]Fatal Error Mask.For SMLbit[0]：smxt fatal error
                                        mask;bit[1]：smmc_l fatal error maskbit[2]：smeg_core fatal error
                                        maskbit[3~6]：Reserved.For SMFbit[0]：smxr fatal e rror mask;bit[1]：smxt fatal
                                        error mask;bit[2]：smmc_f fatal error maskbit[3]：smeg_core 3 fatal error
                                        maskbit[4]：smeg_core 2 fatal error maskbit[5]：smeg_core 1 fa tal error
                                        maskbit[6]：smeg_core 0 fatal error mask7 fatal error source for SMF and 3 fatal
                                        error source for SML, SW can mask the fatal error of each source respe
                                        ctively.1'b0: Mask the fatal error;1'b1: Unmask the fatal error */
        unsigned int rpCrtErrInjReq : 1;   /* * [30:30]ECC crt err injection requestion;err injection start when posedge
                                        of this bit is detected; After Err injection start, err is injected when a memory
                                        read is issu ed to the memory.Enable memory check, when use this err inection
                                        function. */
        unsigned int rpUncrtErrInjReq : 1; /* * [31:31]ECC uncrt err injection requestion;err injection start when
                                        posedge of this bit is detected; After Err injection start, err is injected when
                                        a memory read is is sued to the memory.Enable memory check, when use this err
                                        inection function. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_CFG1_U;

/* **
 * Union name :    SMXR_CFG0
 * @brief               SMXR cofigure registers
 * Description:
 */
typedef union tagUnSmxrCfg0 {
    struct tagStSmxrCfg0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int rpFairnessNum : 16; /* * [31:16]This is the flit numbers to the same smeg_core before fairness
                                          * scheme is execute
                                          */
        unsigned int rpFairnessEn : 1; /* * [15:15]1:  turn on XR arbiter fairness0:  do not use XR arbiter fairness */
        unsigned int reserved : 1;     /* * [14:14] */
        unsigned int rpLbQuLdWqe : 2;  /* * [13:12]load balance for ROCE load WQE API from QU:2'b00 - to infra
                                        * pipeline02'b01 - to infra pipeline12'b10 - to infra pipeline22'b11 - to infra
                                        * pipeline3
                                        */
        unsigned int rpInstIdQuLdWqe : 5; /* * [11:7]instance id for  ROCE load WQE API from QU */
        unsigned int rpLbMqm : 2;     /* * [6:5]load balance for API from MQM:2'b00 - to infra pipeline02'b01 - to infra
                                       * pipeline12'b10 - to infra pipeline22'b11 - to infra pipeline3
                                       */
        unsigned int rpInstIdMqm : 5; /* * [4:0]instance id for API from MQM */
#else
        unsigned int rpInstIdMqm : 5;      /* * [4:0]instance id for API from MQM */
        unsigned int rpLbMqm : 2; /* * [6:5]load balance for API from MQM:2'b00 - to infra pipeline02'b01 - to infra
                                   * pipeline12'b10 - to infra pipeline22'b11 - to infra pipeline3
                                   */
        unsigned int rpInstIdQuLdWqe : 5; /* * [11:7]instance id for  ROCE load WQE API from QU */
        unsigned int rpLbQuLdWqe : 2;     /* * [13:12]load balance for ROCE load WQE API from QU:2'b00 - to infra
                                           * pipeline02'b01 - to infra pipeline12'b10 - to infra pipeline22'b11 - to infra
                                           * pipeline3
                                           */
        unsigned int reserved : 1;        /* * [14:14] */
        unsigned int rpFairnessEn : 1; /* * [15:15]1:  turn on XR arbiter fairness0:  do not use XR arbiter fairness */
        unsigned int rpFairnessNum : 16; /* * [31:16]This is the flit numbers to the same smeg_core before fairness
                                          * scheme is execute
                                          */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_CFG0_U;

/* **
* Union name :    SMXT_CFG
* @brief               This is the Smart Memory Infra Cross Transmission (SMXT) module configuration register.  The
software use this register for debug.

* Description:
*/
typedef union tagUnSmxtCfg {
    struct tagStSmxtCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 25; /* * [31:7]reserved */
        unsigned int capStart : 1;  /* * [6:6]capture api data start; a posedge of this signal triggle a capture action;
                                     * start capture after all capture mode/match fields are configure
                                     */
        unsigned int regCapChSel : 2; /* * [5:4]Capture data source selection.0: send captured message data from ring
                                   request channel to capture data.1: send captured message data from ring response
                                   channel t o capture data.2: RSV in SML; SMF: send captured message data from to_tile0
                                   channel to capture data.3: RSV in SML; SMF: send captured message data from to_tile1
                                    channel to capture data. */
        unsigned int disTxEgTl1 : 1;  /* * [3:3]disable service for feature engine message transmission to tile1 direct
                                   channel . This is for debug .1: disable.0: enable. Note:only used for debug,users
                                   sh ould know the api counts before config this bit. */
        unsigned int disTxEgTl0 : 1;  /* * [2:2]disable service for feature engine message transmission to tile0 direct
                                   channel . This is for debug .1: disable.0: enable. Note:only used for debug,users
                                   sh ould know the api counts before config this bit. */
        unsigned int disTxMc : 1; /* * [1:1]disable service for smmc message transmission . This is for debug .1:
                               disable.0: enable.Note:only used for debug,users should know the api counts before con
                               fig this bit. */
        unsigned int disTxEg : 1; /* * [0:0]disable service for feature engine message transmission to ting. This is for
                                debug .1: disable.0: enable. Note:only used for debug,users should know the api
                                counts before config this bit. */
#else
        unsigned int disTxEg : 1; /* * [0:0]disable service for feature engine message transmission to ting. This is for
                                debug .1: disable.0: enable. Note:only used for debug,users should know the api
                                counts before config this bit. */
        unsigned int disTxMc : 1; /* * [1:1]disable service for smmc message transmission . This is for debug .1:
                               disable.0: enable.Note:only used for debug,users should know the api counts before con
                               fig this bit. */
        unsigned int disTxEgTl0 : 1;  /* * [2:2]disable service for feature engine message transmission to tile0 direct
                                   channel . This is for debug .1: disable.0: enable. Note:only used for debug,users
                                   sh ould know the api counts before config this bit. */
        unsigned int disTxEgTl1 : 1;  /* * [3:3]disable service for feature engine message transmission to tile1 direct
                                   channel . This is for debug .1: disable.0: enable. Note:only used for debug,users
                                   sh ould know the api counts before config this bit. */
        unsigned int regCapChSel : 2; /* * [5:4]Capture data source selection.0: send captured message data from ring
                                   request channel to capture data.1: send captured message data from ring response
                                   channel t o capture data.2: RSV in SML; SMF: send captured message data from to_tile0
                                   channel to capture data.3: RSV in SML; SMF: send captured message data from to_tile1
                                    channel to capture data. */
        unsigned int capStart : 1;  /* * [6:6]capture api data start; a posedge of this signal triggle a capture action;
                                     * start capture after all capture mode/match fields are configure
                                     */
        unsigned int reserved : 25; /* * [31:7]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CFG_U;

/* **
 * Union name :    SMXR_TM_GRT01
 * @brief               Timer Group Routing table   element 0 and 1
 * Description:
 */
typedef union tagUnSmxrTmGrt01 {
    struct tagStSmxrTmGrt01 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int rpTmGrt1 : 13; /* * [28:16]As same as configure for group0 */
        unsigned int reserved1 : 3; /* * [15:13]reserved */
        unsigned int rpTmGrt0 : 13; /* * [12:0]Timer routing table configure for group0:bit12:11 - Load balance factor
                                indicates which engine core this timer group is instanced to.    00: send to core 0    0
                                1: send to core 1    10: send to core 2    11: send to core 3bit10:9  - This timer group
                                belong to which hostbit8:5   - Indicates which PF this timer group is m apped into.
                                Default 0~15 is used as global PPF for up to 4 hostsbit4:0   - Indicates which instance
                                ID is for timer engine in target engine core.
                                 */
#else
        unsigned int rpTmGrt0 : 13; /* * [12:0]Timer routing table configure for group0:bit12:11 - Load balance factor
                                indicates which engine core this timer group is instanced to.    00: send to core 0    0
                                1: send to core 1    10: send to core 2    11: send to core 3bit10:9  - This timer group
                                belong to which hostbit8:5   - Indicates which PF this timer group is m apped into.
                                Default 0~15 is used as global PPF for up to 4 hostsbit4:0   - Indicates which instance
                                ID is for timer engine in target engine core.
                                 */
        unsigned int reserved1 : 3; /* * [15:13]reserved */
        unsigned int rpTmGrt1 : 13; /* * [28:16]As same as configure for group0 */
        unsigned int reserved0 : 3; /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_TM_GRT01_U;

/* **
 * Union name :    SMXR_TM_GRT23
 * @brief               Timer Group Routing table   element 2 and 3
 * Description:
 */
typedef union tagUnSmxrTmGrt23 {
    struct tagStSmxrTmGrt23 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int rpTmGrt3 : 13; /* * [28:16]As same as configure for group0 */
        unsigned int reserved1 : 3; /* * [15:13]reserved */
        unsigned int rpTmGrt2 : 13; /* * [12:0]As same as configure for group0 */
#else
        unsigned int rpTmGrt2 : 13; /* * [12:0]As same as configure for group0 */
        unsigned int reserved1 : 3; /* * [15:13]reserved */
        unsigned int rpTmGrt3 : 13; /* * [28:16]As same as configure for group0 */
        unsigned int reserved0 : 3; /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_TM_GRT23_U;

/* **
 * Union name :    SMRT_INT_VECTOR
 * @brief
 * Description:
 */
typedef union tagUnSmrtIntVector {
    struct tagStSmrtIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                     * register0:interrupt disable1:interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;       /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                        * register0:interrupt disable1:interrupt enable
                                        */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMRT_INT_VECTOR_U;

/* **
 * Union name :    SMRT_INT
 * @brief               SMRT interrupt data
 * Description:
 */
typedef union tagUnSmrtInt {
    struct tagStSmrtInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 13;     /* * [15:3]reserved */
        unsigned int intData : 3;       /* * [2:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 3;   /* * [2:0]interrupt masked field,it is the collection of the error bits from the
                                     * corresponding error registers on the sheet
                                     */
        unsigned int reserved : 13; /* * [15:3]reserved */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMRT_INT_U;

/* **
 * Union name :    SMRT_INT_MASK
 * @brief               SMIR interrupt mask configuration
 * Description:
 */
typedef union tagUnSmrtIntMask {
    struct tagStSmrtIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 13;     /* * [15:3]reserved */
        unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 13;     /* * [15:3]reserved */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMRT_INT_MASK_U;

/* **
 * Union name :    SMXR_REQ_MEM_CRT_ERR
 * @brief               ECC correctable memory detected on SMXR request memory
 * Description:
 */
typedef union tagUnSmxrReqMemCrtErr {
    struct tagStSmxrReqMemCrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                              Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1
                              req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                              Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1
                              req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_REQ_MEM_CRT_ERR_U;

/* **
 * Union name :    SMXR_REQ_MEM_UNCRT_ERR
 * @brief               ECC un-correctable memory detected on SMXR request memory
 * Description:
 */
typedef union tagUnSmxrReqMemUncrtErr {
    struct tagStSmxrReqMemUncrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                              Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1
                              req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                              Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1
                              req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_REQ_MEM_UNCRT_ERR_U;

/* **
 * Union name :    SMXR_MISS_SOP_EOP_ERR
 * @brief               SMXR received miss EOP API
 * Description:
 */
typedef union tagUnSmxrMissSopEopErr {
    struct tagStSmxrMissSopEopErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.31:25
                                - thread id;24:19 - src_tag_h;18:14 - src;13:8  - rsv ;7     - tile16     - tile05
                                - ring resp4     - ring rqst3     - miss eop2     - miss sop */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.31:25
                                - thread id;24:19 - src_tag_h;18:14 - src;13:8  - rsv ;7     - tile16     - tile05
                                - ring resp4     - ring rqst3     - miss eop2     - miss sop */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_MISS_SOP_EOP_ERR_U;

/* **
 * Union name :    SMXR_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmxrIndrectCtrl {
    struct tagStSmxrIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxrIndirVld : 1;   /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
        unsigned int smxrIndirMode : 1;  /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smxrIndirStat : 2;  /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smxrIndirTab : 4;   /* * [27:24]It specifies memory group or table. 4’b0000: DBLB(Doorbeel
                                          * loadbalance table), only in SMF4'b0001: API_CAP: SMXT capture API data （read
                                          * only）others:reserved
                                          */
        unsigned int smxrIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address
                                     in one group or internal address of the table.bit[5:0] memory address DBLB: only
                                     bit 4:0 is v alidAPI_CAP: bit[5:2] flit number, bit[1:0] API DW: 00-flit[127:96],
                                     01-flit[95:64], 10-flit[63:32], 11-flit[31:0]
                                      */
#else
        unsigned int smxrIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address
                                     in one group or internal address of the table.bit[5:0] memory address DBLB: only
                                     bit 4:0 is v alidAPI_CAP: bit[5:2] flit number, bit[1:0] API DW: 00-flit[127:96],
                                     01-flit[95:64], 10-flit[63:32], 11-flit[31:0]
                                      */
        unsigned int smxrIndirTab : 4;   /* * [27:24]It specifies memory group or table. 4’b0000: DBLB(Doorbeel
                                          * loadbalance table), only in SMF4'b0001: API_CAP: SMXT capture API data （read
                                          * only）others:reserved
                                          */
        unsigned int smxrIndirStat : 2;  /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smxrIndirMode : 1;  /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smxrIndirVld : 1;   /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_INDRECT_CTRL_U;

/* **
 * Union name :    SMXR_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmxrIndrectTimeout {
    struct tagStSmxrIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxrIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smxrIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMXR_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmxrIndrectData {
    struct tagStSmxrIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxrIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#else
        unsigned int smxrIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_INDRECT_DATA_U;

/* **
* Union name :    SMXT_CAP_CFG
* @brief               smxt capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.(need to enable per field via <cap_sel _en>
in <smxr_en_cnt> )
* Description:
*/
typedef union tagUnSmxtCapCfg {
    struct tagStSmxtCapCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int capMode : 1;        /* * [31:31]capture mode control register. 0:capture mode disable.smir will not
                                      capture any message.1:capture mode enable.smir will compare the selected fields,only the
                                      mes sages matched with all selected fields will be captured. */
        unsigned int reserved : 17;      /* * [30:14] */
        unsigned int flit0127123Msk : 5; /* * [13:9]flit0 bit127~bit123 capture mask. 1:corresponding bit must match
                                          * when capture.0:don't care whether corresponding bit match when capture.
                                          */
        unsigned int flit0127123 : 5;    /* * [8:4]flit0 bit127~bit123 field to capture . */
        unsigned int capDnidEn : 1;      /* * [3:3]Condition fields enable according to match fields in registers
                                       <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                       <dst_node_id> field match according field in message. 0 ,No need to match this field
                                       .This field's capture valid..
                                       */
        unsigned int capThdIdEn : 1;     /* * [2:2]Condition fields enable according to match fields in registers
                                      <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      <dst_thd_id> field in message match according field in message. 0 ,No need to match
                                      this field .This field's capture valid..
                                       */
        unsigned int capTagHEn : 1;      /* * [1:1]Condition fields enable according to match fields in registers
                                      <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      <dst_tag_h> field i n message match according field in message. 0 ,No need to match
                                      this field .This field's capture valid..
                                       */
        unsigned int capTagLEn : 1;      /* * [0:0]Condition fields enable according to match fields in registers
                                      <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      <dst_tag_l> field i n message match according field in message. 0 ,No need to match
                                      this field .This field's capture valid..
                                       */
#else
        unsigned int capTagLEn : 1;      /* * [0:0]Condition fields enable according to match fields in registers
                                      <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      <dst_tag_l> field i n message match according field in message. 0 ,No need to match
                                      this field .This field's capture valid..
                                       */
        unsigned int capTagHEn : 1;      /* * [1:1]Condition fields enable according to match fields in registers
                                      <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      <dst_tag_h> field i n message match according field in message. 0 ,No need to match
                                      this field .This field's capture valid..
                                       */
        unsigned int capThdIdEn : 1;     /* * [2:2]Condition fields enable according to match fields in registers
                                      <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      <dst_thd_id> field in message match according field in message. 0 ,No need to match
                                      this field .This field's capture valid..
                                       */
        unsigned int capDnidEn : 1;      /* * [3:3]Condition fields enable according to match fields in registers
                                       <SMXT_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                       <dst_node_id> field match according field in message. 0 ,No need to match this field
                                       .This field's capture valid..
                                       */
        unsigned int flit0127123 : 5;    /* * [8:4]flit0 bit127~bit123 field to capture . */
        unsigned int flit0127123Msk : 5; /* * [13:9]flit0 bit127~bit123 capture mask. 1:corresponding bit must match
                                          * when capture.0:don't care whether corresponding bit match when capture.
                                          */
        unsigned int reserved : 17;      /* * [30:14] */
        unsigned int capMode : 1;        /* * [31:31]capture mode control register. 0:capture mode disable.smir will not
                                      capture any message.1:capture mode enable.smir will compare the selected fields,only the
                                      mes sages matched with all selected fields will be captured. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CAP_CFG_U;

/* **
* Union name :    SMXT_CAP_FIELD_CFG
* @brief               SMXT capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.(need to enable per field via <cap_sel _en>
in <smxr_en_cnt> )
* Description:
*/
typedef union tagUnSmxtCapFieldCfg {
    struct tagStSmxtCapFieldCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 1; /* * [31:31]reserved */
        unsigned int dstNdId : 6;  /* * [30:25]<dst_node_id> field to be matchedbit30 is RSV in 1822 */
        unsigned int dstThdId : 7; /* * [24:18]<dst_thd_id> field to be matched */
        unsigned int dstTagH : 6;  /* * [17:12]<dst_tag_h> field to be matched. */
        unsigned int dstTagL : 12; /* * [11:0]<dst_tag_l> field to be matched.For response API, only match low 5 bit,
                                    * which is src field for response API
                                    */
#else
        unsigned int dstTagL : 12;   /* * [11:0]<dst_tag_l> field to be matched.For response API, only match low 5 bit,
                                      * which is src field for response API
                                      */
        unsigned int dstTagH : 6;    /* * [17:12]<dst_tag_h> field to be matched. */
        unsigned int dstThdId : 7;   /* * [24:18]<dst_thd_id> field to be matched */
        unsigned int dstNdId : 6;    /* * [30:25]<dst_node_id> field to be matchedbit30 is RSV in 1822 */
        unsigned int reserved : 1;   /* * [31:31]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CAP_FIELD_CFG_U;

/* **
* Union name :    SMXT_CNT_CFG0
* @brief               SMXT mappable event counter controal . The software use this control to configure expected
counter mapping .

* Description:
*/
typedef union tagUnSmxtCntCfg0 {
    struct tagStSmxtCntCfg0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 7; /* * [31:25]reserved */
        unsigned int
            smxtEnCnt1 : 9; /* * [24:16]Couter source select vector for physical counter2. software can configure this
                         register to decide which counter should be counted into physical counter 2.bit_8: counter
                         enable1'b0:disable counting.1'b1:enable counting.bit[7:6]: channel selection1'b0:this counter
                         will only count the request channel to ring.1'b1:this cou nter will only count the response
                         channel to ring.1'b2:this counter will only count the to_tile0 channel.1'b3:this counter will
                         only count the to_tile1 channel. bit_5:capture Conditional count enable . This is used for
                         debug .When Software enable this field, then only messages matched with  capture condition
                         inside regiser < SMXT_cap_cfg>  will trigger counting. Otherwise ,counter will be triggerd for
                         all kinds of messages . 1 : count only when message match capture trigge r condition.0 : count
                         for all messages.bit[4:0]:counter input selection,config one value to choose which type you
                         want count:5'h0:flits send out from smeg1 of i nfra 05'h1:messages send out from smeg1 of infra
                         05'h2: flits send out from smeg1 of infra 15'h3: messages send out from smeg1 of infra
                         15'h4:flits send out fro m smeg1 of infra 25'h5:messages send out from smeg1 of infra 25'h6:
                         flits send out from smeg1 of infra 35'h7: messages send out from smeg1 of infra 35'h8: flits
                          send out from smmc5'h9: messages send out from smmc 5'ha:the summation of flits from smeg1 +
                         smmc5'hb:the summation of messages from smeg1 + smmc5'hc:flits wit h E0 from smeg1 of infra
                         0.5'hd:messages with E0 from smeg1 of infra 0. （counter when message EOP with E0）5'he:flits
                         with E0 from smeg1 of infra 1.5'hf:messages with E0 from smeg1 of infra 1. （counter when
                         message EOP with E0）5'h10:flits with E0 from smeg1 of infra 2.5'h11:messages with E0 from
                         smeg1 of infra 2.（counte r when message EOP with E0）5'h12:flits with E0 from smeg1 of
                         infra 3.5'h13:messages with E0 from smeg1 of infra 3.（counter when message EOP with
                         E0）5'h14:the su mmation of sop from smeg1+smmc out5'h15:the summation of eop from smeg1+smmc
                         out5'h16:sop send out from smeg1 infra 0.5'h17:eop send out from smeg1 infra 0.5'h1 8:sop send
                         out from smeg1 infra 1.5'h19:eop send out from smeg1 infra 1.5'h1a:sop send out from smeg1
                         infra 2.5'h1b:eop send out from smeg1 infra 2.5'h1c:sop se nd out from smeg1 infra 3.5'h1d:eop
                         send out from smeg1 infra 3.5'h1e:sop send out from smmc5'h1f:eop send out from smmc
                          */
        unsigned int reserved1 : 7;  /* * [15:9]reserved */
        unsigned int smxtEnCnt0 : 9; /* * [8:0]as same as SMXT_en_cnt_1 */
#else
        unsigned int smxtEnCnt0 : 9; /* * [8:0]as same as SMXT_en_cnt_1 */
        unsigned int reserved1 : 7;  /* * [15:9]reserved */
        unsigned int
            smxtEnCnt1 : 9; /* * [24:16]Couter source select vector for physical counter2. software can configure this
                         register to decide which counter should be counted into physical counter 2.bit_8: counter
                         enable1'b0:disable counting.1'b1:enable counting.bit[7:6]: channel selection1'b0:this counter
                         will only count the request channel to ring.1'b1:this cou nter will only count the response
                         channel to ring.1'b2:this counter will only count the to_tile0 channel.1'b3:this counter will
                         only count the to_tile1 channel. bit_5:capture Conditional count enable . This is used for
                         debug .When Software enable this field, then only messages matched with  capture condition
                         inside regiser < SMXT_cap_cfg>  will trigger counting. Otherwise ,counter will be triggerd for
                         all kinds of messages . 1 : count only when message match capture trigge r condition.0 : count
                         for all messages.bit[4:0]:counter input selection,config one value to choose which type you
                         want count:5'h0:flits send out from smeg1 of i nfra 05'h1:messages send out from smeg1 of infra
                         05'h2: flits send out from smeg1 of infra 15'h3: messages send out from smeg1 of infra
                         15'h4:flits send out fro m smeg1 of infra 25'h5:messages send out from smeg1 of infra 25'h6:
                         flits send out from smeg1 of infra 35'h7: messages send out from smeg1 of infra 35'h8: flits
                          send out from smmc5'h9: messages send out from smmc 5'ha:the summation of flits from smeg1 +
                         smmc5'hb:the summation of messages from smeg1 + smmc5'hc:flits wit h E0 from smeg1 of infra
                         0.5'hd:messages with E0 from smeg1 of infra 0. （counter when message EOP with E0）5'he:flits
                         with E0 from smeg1 of infra 1.5'hf:messages with E0 from smeg1 of infra 1. （counter when
                         message EOP with E0）5'h10:flits with E0 from smeg1 of infra 2.5'h11:messages with E0 from
                         smeg1 of infra 2.（counte r when message EOP with E0）5'h12:flits with E0 from smeg1 of
                         infra 3.5'h13:messages with E0 from smeg1 of infra 3.（counter when message EOP with
                         E0）5'h14:the su mmation of sop from smeg1+smmc out5'h15:the summation of eop from smeg1+smmc
                         out5'h16:sop send out from smeg1 infra 0.5'h17:eop send out from smeg1 infra 0.5'h1 8:sop send
                         out from smeg1 infra 1.5'h19:eop send out from smeg1 infra 1.5'h1a:sop send out from smeg1
                         infra 2.5'h1b:eop send out from smeg1 infra 2.5'h1c:sop se nd out from smeg1 infra 3.5'h1d:eop
                         send out from smeg1 infra 3.5'h1e:sop send out from smmc5'h1f:eop send out from smmc
                          */
        unsigned int reserved0 : 7;  /* * [31:25]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CNT_CFG0_U;

/* **
* Union name :    SMXT_CNT_CFG1
* @brief               SMXT mappable event counter controal . The software use this control to configure expected
counter mapping .

* Description:
*/
typedef union tagUnSmxtCntCfg1 {
    struct tagStSmxtCntCfg1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 7;  /* * [31:25]reserved */
        unsigned int smxtEnCnt3 : 9; /* * [24:16]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */
        unsigned int reserved1 : 7;  /* * [15:9]reserved */
        unsigned int smxtEnCnt2 : 9; /* * [8:0]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */
#else
        unsigned int smxtEnCnt2 : 9; /* * [8:0]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */
        unsigned int reserved1 : 7;  /* * [15:9]reserved */
        unsigned int smxtEnCnt3 : 9; /* * [24:16]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */
        unsigned int reserved0 : 7;  /* * [31:25]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CNT_CFG1_U;

/* **
* Union name :    SMXT_CNT0
* @brief               SMXT physical counter 0.software can enable which events to be counted into it via field
<SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> .

* Description:
*/
typedef union tagUnSmxtCnt0 {
    struct tagStSmxtCnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxtCnt0 : 32; /* * [31:0]SMXT physical counter 0.software can enable which events to be counted
                                     * into it via field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> .
                                     */
#else
        unsigned int smxtCnt0 : 32;  /* * [31:0]SMXT physical counter 0.software can enable which events to be counted
                                      * into it via field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> .
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CNT0_U;

/* **
* Union name :    SMXT_CNT1
* @brief               SMXT physical counter 1.software can enable which events to be counted into it via field
<SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> .

* Description:
*/
typedef union tagUnSmxtCnt1 {
    struct tagStSmxtCnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxtCnt1 : 32; /* * [31:0]SMXT physical counter 1.software can enable which events to be counted
                                     * into it via field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> .
                                     */
#else
        unsigned int smxtCnt1 : 32;  /* * [31:0]SMXT physical counter 1.software can enable which events to be counted
                                      * into it via field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> .
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CNT1_U;

/* **
* Union name :    SMXT_CNT2
* @brief               SMXT physical counter 2.software can enable which events to be counted into it via field
<SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> .

* Description:
*/
typedef union tagUnSmxtCnt2 {
    struct tagStSmxtCnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxtCnt2 : 32; /* * [31:0]SMXT physical counter 2.software can enable which events to be counted
                                     * into it via field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> .
                                     */
#else
        unsigned int smxtCnt2 : 32;  /* * [31:0]SMXT physical counter 2.software can enable which events to be counted
                                      * into it via field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> .
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CNT2_U;

/* **
* Union name :    SMXT_CNT3
* @brief               SMXT physical counter 3.software can enable which events to be counted into it via field
<SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> .

* Description:
*/
typedef union tagUnSmxtCnt3 {
    struct tagStSmxtCnt3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxtCnt3 : 32; /* * [31:0]SMXT physical counter 3.software can enable which events to be counted
                                     * into it via field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> .
                                     */
#else
        unsigned int smxtCnt3 : 32;  /* * [31:0]SMXT physical counter 3.software can enable which events to be counted
                                      * into it via field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> .
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CNT3_U;

/* **
 * Union name :    SMXT_CRDT_CNT
 * @brief               smxt credit counter CTP registers
 * Description:
 */
typedef union tagUnSmxtCrdtCnt {
    struct tagStSmxtCrdtCnt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16;   /* * [31:16]reserved. */
        unsigned int ringRqstCtp : 3; /* * [15:13]SMXT credit counter CTP registers for ring request channel*NOTE: the
                                       * default value is 0 in SML
                                       */
        unsigned int ringRespCtp : 3; /* * [12:10]SMXT credit counter CTP registers for ring response channel*NOTE: the
                                       * default value is 0 in SML
                                       */
        unsigned int tl0Ctp : 5; /* * [9:5]SMXT credit counter CTP registers for tile0*NOTE: the default value is 0 in
                                    SML */
        unsigned int tl1Ctp : 5; /* * [4:0]SMXT credit counter CTP registers for tile1*NOTE: the default value is 0 in
                                    SML */
#else
        unsigned int tl1Ctp : 5; /* * [4:0]SMXT credit counter CTP registers for tile1*NOTE: the default value is 0 in
                                    SML */
        unsigned int tl0Ctp : 5; /* * [9:5]SMXT credit counter CTP registers for tile0*NOTE: the default value is 0 in
                                    SML */
        unsigned int ringRespCtp : 3; /* * [12:10]SMXT credit counter CTP registers for ring response channel*NOTE: the
                                       * default value is 0 in SML
                                       */
        unsigned int ringRqstCtp : 3; /* * [15:13]SMXT credit counter CTP registers for ring request channel*NOTE: the
                                       * default value is 0 in SML
                                       */
        unsigned int reserved : 16;   /* * [31:16]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CRDT_CNT_U;

/* **
 * Union name :    SMXT_FIFO_DEPTH0
 * @brief               FIFO depth CTP registers for SMXT FIFOs for SMF infra1 and infra0
 * Description:
 */
typedef union tagUnSmxtFifoDepth0 {
    struct tagStSmxtFifoDepth0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 29;      /* * [63:35]reserved. */
        unsigned long long mcCtp : 3;          /* * [34:32]SMXT FIFO depth CTP registers for SMMC */
        unsigned long long if1RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */
        unsigned long long if1RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */
        unsigned long long if1Tl0Ctp : 4;      /* * [23:20]SMXT FIFO depth CTP registers for tile0 */
        unsigned long long if1Tl1Ctp : 4;      /* * [19:16]SMXT FIFO depth CTP registers for tile1 */
        unsigned long long if0RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */
        unsigned long long if0RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */
        unsigned long long if0Tl0Ctp : 4;      /* * [7:4]SMXT FIFO depth CTP registers for tile0 */
        unsigned long long if0Tl1Ctp : 4;      /* * [3:0]SMXT FIFO depth CTP registers for tile1 */
#else
        unsigned long long if0Tl1Ctp : 4;      /* * [3:0]SMXT FIFO depth CTP registers for tile1 */
        unsigned long long if0Tl0Ctp : 4;      /* * [7:4]SMXT FIFO depth CTP registers for tile0 */
        unsigned long long if0RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */
        unsigned long long if0RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */
        unsigned long long if1Tl1Ctp : 4;      /* * [19:16]SMXT FIFO depth CTP registers for tile1 */
        unsigned long long if1Tl0Ctp : 4;      /* * [23:20]SMXT FIFO depth CTP registers for tile0 */
        unsigned long long if1RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */
        unsigned long long if1RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */
        unsigned long long mcCtp : 3;          /* * [34:32]SMXT FIFO depth CTP registers for SMMC */
        unsigned long long reserved : 29;      /* * [63:35]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMXT_FIFO_DEPTH0_U;

/* **
 * Union name :    SMXT_FIFO_DEPTH1
 * @brief               FIFO depth CTP registers for SMXT FIFOs for SMF infra3 and Infra2
 * Description:
 */
typedef union tagUnSmxtFifoDepth1 {
    struct tagStSmxtFifoDepth1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int if3RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */
        unsigned int if3RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */
        unsigned int if3Tl0Ctp : 4;      /* * [23:20]SMXT FIFO depth CTP registers for tile0 */
        unsigned int if3Tl1Ctp : 4;      /* * [19:16]SMXT FIFO depth CTP registers for tile1 */
        unsigned int if2RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */
        unsigned int if2RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */
        unsigned int if2Tl0Ctp : 4;      /* * [7:4]SMXT FIFO depth CTP registers for tile0 */
        unsigned int if2Tl1Ctp : 4;      /* * [3:0]SMXT FIFO depth CTP registers for tile1 */
#else
        unsigned int if2Tl1Ctp : 4;            /* * [3:0]SMXT FIFO depth CTP registers for tile1 */
        unsigned int if2Tl0Ctp : 4;            /* * [7:4]SMXT FIFO depth CTP registers for tile0 */
        unsigned int if2RingRespCtp : 4;       /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */
        unsigned int if2RingRqstCtp : 4;       /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */
        unsigned int if3Tl1Ctp : 4;            /* * [19:16]SMXT FIFO depth CTP registers for tile1 */
        unsigned int if3Tl0Ctp : 4;            /* * [23:20]SMXT FIFO depth CTP registers for tile0 */
        unsigned int if3RingRespCtp : 4;       /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */
        unsigned int if3RingRqstCtp : 4;       /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_FIFO_DEPTH1_U;

/* **
 * Union name :    TL0_Q_DEP
 * @brief               queue depth for API from TILE0 in SMXR
 * Description:
 */
typedef union tagUnTl0QDep {
    struct tagStTl0QDep {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 2; /* * [31:30]reserved */
        unsigned int l3Ctp : 6;     /* * [29:24]flit number in queue to smeg_core3 */
        unsigned int reserved1 : 2; /* * [23:22]reserved */
        unsigned int l2Ctp : 6;     /* * [21:16]flit number in queue to smeg_core2 */
        unsigned int reserved2 : 2; /* * [15:14]reserved */
        unsigned int l1Ctp : 6;     /* * [13:8]flit number in queue to smeg_core1 */
        unsigned int reserved3 : 2; /* * [7:6]reserved */
        unsigned int l0Ctp : 6;     /* * [5:0]flit number in queue to smeg_core0 */
#else
        unsigned int l0Ctp : 6;                /* * [5:0]flit number in queue to smeg_core0 */
        unsigned int reserved3 : 2;            /* * [7:6]reserved */
        unsigned int l1Ctp : 6;                /* * [13:8]flit number in queue to smeg_core1 */
        unsigned int reserved2 : 2;            /* * [15:14]reserved */
        unsigned int l2Ctp : 6;                /* * [21:16]flit number in queue to smeg_core2 */
        unsigned int reserved1 : 2;            /* * [23:22]reserved */
        unsigned int l3Ctp : 6;                /* * [29:24]flit number in queue to smeg_core3 */
        unsigned int reserved0 : 2;            /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_TL0_Q_DEP_U;

/* **
 * Union name :    TL1_Q_DEP
 * @brief               queue depth for API from TILE1 in SMXR
 * Description:
 */
typedef union tagUnTl1QDep {
    struct tagStTl1QDep {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 2; /* * [31:30]reserved */
        unsigned int l3Ctp : 6;     /* * [29:24]flit number in queue to smeg_core3 */
        unsigned int reserved1 : 2; /* * [23:22]reserved */
        unsigned int l2Ctp : 6;     /* * [21:16]flit number in queue to smeg_core2 */
        unsigned int reserved2 : 2; /* * [15:14]reserved */
        unsigned int l1Ctp : 6;     /* * [13:8]flit number in queue to smeg_core1 */
        unsigned int reserved3 : 2; /* * [7:6]reserved */
        unsigned int l0Ctp : 6;     /* * [5:0]flit number in queue to smeg_core0 */
#else
        unsigned int l0Ctp : 6;                /* * [5:0]flit number in queue to smeg_core0 */
        unsigned int reserved3 : 2;            /* * [7:6]reserved */
        unsigned int l1Ctp : 6;                /* * [13:8]flit number in queue to smeg_core1 */
        unsigned int reserved2 : 2;            /* * [15:14]reserved */
        unsigned int l2Ctp : 6;                /* * [21:16]flit number in queue to smeg_core2 */
        unsigned int reserved1 : 2;            /* * [23:22]reserved */
        unsigned int l3Ctp : 6;                /* * [29:24]flit number in queue to smeg_core3 */
        unsigned int reserved0 : 2;            /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_TL1_Q_DEP_U;

/* **
 * Union name :    RQST_Q_DEP
 * @brief               queue depth for API from RING request channel in SMXR
 * Description:
 */
typedef union tagUnRqstQDep {
    struct tagStRqstQDep {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16; /* * [31:16]reserved */
        unsigned int l3Ctp : 4;     /* * [15:12]flit number in queue to smeg_core3 */
        unsigned int l2Ctp : 4;     /* * [11:8]flit number in queue to smeg_core2 */
        unsigned int l1Ctp : 4;     /* * [7:4]flit number in queue to smeg_core1 */
        unsigned int l0Ctp : 4;     /* * [3:0]flit number in queue to smeg_core0 */
#else
        unsigned int l0Ctp : 4;                /* * [3:0]flit number in queue to smeg_core0 */
        unsigned int l1Ctp : 4;                /* * [7:4]flit number in queue to smeg_core1 */
        unsigned int l2Ctp : 4;                /* * [11:8]flit number in queue to smeg_core2 */
        unsigned int l3Ctp : 4;                /* * [15:12]flit number in queue to smeg_core3 */
        unsigned int reserved : 16;            /* * [31:16]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_RQST_Q_DEP_U;

/* **
 * Union name :    RSP_Q_DEP
 * @brief               queue depth for API from RING request channel in SMXR
 * Description:
 */
typedef union tagUnRspQDep {
    struct tagStRspQDep {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 12; /* * [31:20]reserved */
        unsigned int l4Ctp : 4;     /* * [19:16]flit number in queue to SMMC */
        unsigned int l3Ctp : 4;     /* * [15:12]flit number in queue to smeg_core3 */
        unsigned int l2Ctp : 4;     /* * [11:8]flit number in queue to smeg_core2 */
        unsigned int l1Ctp : 4;     /* * [7:4]flit number in queue to smeg_core1 */
        unsigned int l0Ctp : 4;     /* * [3:0]flit number in queue to smeg_core0 */
#else
        unsigned int l0Ctp : 4;                /* * [3:0]flit number in queue to smeg_core0 */
        unsigned int l1Ctp : 4;                /* * [7:4]flit number in queue to smeg_core1 */
        unsigned int l2Ctp : 4;                /* * [11:8]flit number in queue to smeg_core2 */
        unsigned int l3Ctp : 4;                /* * [15:12]flit number in queue to smeg_core3 */
        unsigned int l4Ctp : 4;                /* * [19:16]flit number in queue to SMMC */
        unsigned int reserved : 12;            /* * [31:20]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_RSP_Q_DEP_U;

/* **
 * Union name :    RQST_CRDT_CNT
 * @brief               rqst channel credit counter  in SMXR
 * Description:
 */
typedef union tagUnRqstCrdtCnt {
    struct tagStRqstCrdtCnt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 12; /* * [31:20]reserved */
        unsigned int sm3Ctp : 5;    /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm2Ctp : 5;    /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm1Ctp : 5;    /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm0Ctp : 5;    /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
#else
        unsigned int sm0Ctp : 5;    /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm1Ctp : 5;    /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm2Ctp : 5;    /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm3Ctp : 5;    /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int reserved : 12; /* * [31:20]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_RQST_CRDT_CNT_U;

/* **
 * Union name :    RESP_CRDT_CNT
 * @brief               rsponse channel credit counter in SMXR
 * Description:
 */
typedef union tagUnRespCrdtCnt {
    struct tagStRespCrdtCnt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 7; /* * [31:25]reserved */
        unsigned int smmcCtp : 5;  /* * [24:20]credit counter of smmcbinary format *NOTE: the default value is 0 in SML
                                    */
        unsigned int sm3Ctp : 5;   /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the
                                    * credit number *NOTE: the default value is 0 in SML
                                    */
        unsigned int sm2Ctp : 5;   /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the
                                    * credit number *NOTE: the default value is 0 in SML
                                    */
        unsigned int sm1Ctp : 5;   /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the
                                    * credit number *NOTE: the default value is 0 in SML
                                    */
        unsigned int sm0Ctp : 5;   /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the
                                    * credit number *NOTE: the default value is 0 in SML
                                    */
#else
        unsigned int sm0Ctp : 5;    /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm1Ctp : 5;    /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm2Ctp : 5;    /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int sm3Ctp : 5;    /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the
                                     * credit number *NOTE: the default value is 0 in SML
                                     */
        unsigned int smmcCtp : 5;   /* * [24:20]credit counter of smmcbinary format *NOTE: the default value is 0 in SML
                                     */
        unsigned int reserved : 7;  /* * [31:25]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_RESP_CRDT_CNT_U;

/* **
 * Union name :    SMXR_CNT0
 * @brief               Cnt for tile0 direct channel
 * Description:
 */
typedef union tagUnSmxrCnt0 {
    struct tagStSmxrCnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxrCnt0 : 32; /* * [31:0]Cnt for tile0 direct channel */
#else
        unsigned int smxrCnt0 : 32; /* * [31:0]Cnt for tile0 direct channel */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_CNT0_U;

/* **
 * Union name :    SMXR_CNT1
 * @brief               Cnt for tile1 direct channel
 * Description:
 */
typedef union tagUnSmxrCnt1 {
    struct tagStSmxrCnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxrCnt1 : 32; /* * [31:0]Cnt for tile1 direct channel */
#else
        unsigned int smxrCnt1 : 32; /* * [31:0]Cnt for tile1 direct channel */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_CNT1_U;

/* **
 * Union name :    SMXR_CNT2
 * @brief               Cnt for ring request channel
 * Description:
 */
typedef union tagUnSmxrCnt2 {
    struct tagStSmxrCnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxrCnt2 : 32; /* * [31:0]Cnt for ring request channel */
#else
        unsigned int smxrCnt2 : 32; /* * [31:0]Cnt for ring request channel */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_CNT2_U;

/* **
 * Union name :    SMXR_CNT3
 * @brief               Cnt for ring rsponse channel
 * Description:
 */
typedef union tagUnSmxrCnt3 {
    struct tagStSmxrCnt3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smxrCnt3 : 32; /* * [31:0]Cnt for ring rsponse channel */
#else
        unsigned int smxrCnt3 : 32; /* * [31:0]Cnt for ring rsponse channel */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXR_CNT3_U;

/* **
 * Union name :    SMXT_CTP
 * @brief               SMXT CTP registers
 * Description:
 */
typedef union tagUnSmxtCtp {
    struct tagStSmxtCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 31;  /* * [31:1]reserved */
        unsigned int apiCapDone : 1; /* * [0:0]0: API capture not success1: API capture successed */
#else
        unsigned int apiCapDone : 1;   /* * [0:0]0: API capture not success1: API capture successed */
        unsigned int reserved : 31;    /* * [31:1]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMXT_CTP_U;


/* **
 * Union name :    SMIR_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmirVersion {
    struct tagStSmirVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smirVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smirVersion : 32; /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_VERSION_U;

/* **
* Union name :    SMIR_CFG
* @brief               This is the Smart Memory Infra Receive (SMIR) module configuration register. Use this register
for debug.

* Description:
*/
typedef union tagUnSmirCfg {
    struct tagStSmirCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 6;        /* * [31:26]reserved */
        unsigned int rpUncrtErrInjReq : 1; /* * [25:25]ECC uncrt err injection requestion;err injection start when
                                        posedge of this bit is detected; After Err injection start, err is injected when
                                        a memory read is is sued to the memory. Enable memory check, when use this err
                                        inection function. */
        unsigned int rpCrtErrInjReq : 1;   /* * [24:24]ECC crt err injection requestion;err injection start when posedge
                                        of this bit is detected; After Err injection start, err is injected when a memory
                                        read is issu ed to the memory.Enable memory check, when use this err inection
                                        function. */
        unsigned int memRet1n : 1;         /* * [23:23]control of memory pin RET1N */
        unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                     * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int reserved1 : 9; /* * [15:7]reserved */
        unsigned int rpL2nicDbPseudoApiEn : 1; /* * [6:6]L2NIC DB pseudo API enable:1'b1: judge the API TYPE (pseudo or
                                                * not) according to the "pseudo" bit in API;1'b0: All L2NIC DB API is
                                                * regarded as non-pseudo API.
                                                */
        unsigned int memChkEn : 1; /* * [5:5]memory parity check enable.1'b0:disable all memories err check.1'b1:enable
                                    * all memories err check.
                                    */
        unsigned int msbThreadCfg : 1; /* * [4:4]0:msb thread is used as special thread only used in response
                                    channel;1:msb thread is used as normal thread only used in request channel;*NOTE:
                                    This bit and smeg 1.smeg1_cfg0.msb_thread_cfg should be configure the same value */
        unsigned int regCapChSel : 1;  /* * [3:3]capture data selection,used to choose a channel data into
                                    SMIR_CAP_DATA.0: put the caputured data from request channel into SMIR_CAP_DATA. 1:
                                    put the caputured data from response channel into SMIR_CAP_DATA. Note:both request
                                    channel and response channel have capture logic,they can capture message at same
                                    time. The chan
                                    nel selection is used to decide which channel to be displayed to uers. */
        unsigned int simpleHash : 1; /* * [2:2]simple hash computaion select.This bit is used for vefication Verfication
                                  can simulate hash collsion easily via this mode .0: default hardware hash computation.
                                  1 : select lower 64bits of hash key as hash result instead of standard hardware hash
                                  computation.FHT Engine: select first 32bit of hash key (sop[63:32] as hash result;
                                  Stateless Hash:If key size is 10B: select first 64bit of hash key (sop[103:40] as hash
                                  result;if key size is 4B：select all 32bit key：sop [95:64], then u se { key[23:16],
                                  key[31:24], key[7:0], key[15:8], key[31:0]} as hash result;else, select first 64bit of
                                  hash key (sop[95:32] as hash result;Statefull Hash:If ke y size is 42B/26B/10B, select
                                  first 64bit of hash key (sop[79:16] as hash result;If key size is 9B，select first
                                  64bit of hash key (sop[95:32] as hash result;
                                   */
        unsigned int disRxResp : 1;  /* * [1:1]disable receive message from response channel . This bit is used for
                                  debug. Software can stop to receive message from response channel via set this
                                  bit.1: d isable receive message from response channel.0: enable. */
        unsigned int disRxRqst : 1;  /* * [0:0]disable request message from request channel . This bit is used for
                                  debug. Software can stop to receive message from request channel via set this
                                  bit.1: dis able receive message from request channel.0: enable.Note: This bit should
                                  not be config to 1 as csr message cannot be delivered to cnb after request channel is
                                  disabled. */
#else
        unsigned int disRxRqst : 1;    /* * [0:0]disable request message from request channel . This bit is used for
                                    debug. Software can stop to receive message from request channel via set this
                                    bit.1: dis able receive message from request channel.0: enable.Note: This bit should
                                    not be config to 1 as csr message cannot be delivered to cnb after request channel is
                                    disabled. */
        unsigned int disRxResp : 1;    /* * [1:1]disable receive message from response channel . This bit is used for
                                    debug. Software can stop to receive message from response channel via set this
                                    bit.1: d isable receive message from response channel.0: enable. */
        unsigned int simpleHash : 1; /* * [2:2]simple hash computaion select.This bit is used for vefication Verfication
                                  can simulate hash collsion easily via this mode .0: default hardware hash computation.
                                  1 : select lower 64bits of hash key as hash result instead of standard hardware hash
                                  computation.FHT Engine: select first 32bit of hash key (sop[63:32] as hash result;
                                  Stateless Hash:If key size is 10B: select first 64bit of hash key (sop[103:40] as hash
                                  result;if key size is 4B：select all 32bit key：sop [95:64], then u se { key[23:16],
                                  key[31:24], key[7:0], key[15:8], key[31:0]} as hash result;else, select first 64bit of
                                  hash key (sop[95:32] as hash result;Statefull Hash:If ke y size is 42B/26B/10B, select
                                  first 64bit of hash key (sop[79:16] as hash result;If key size is 9B，select first
                                  64bit of hash key (sop[95:32] as hash result;
                                   */
        unsigned int regCapChSel : 1;  /* * [3:3]capture data selection,used to choose a channel data into
                                    SMIR_CAP_DATA.0: put the caputured data from request channel into SMIR_CAP_DATA. 1:
                                    put the caputured data from response channel into SMIR_CAP_DATA. Note:both request
                                    channel and response channel have capture logic,they can capture message at same
                                    time. The chan
                                    nel selection is used to decide which channel to be displayed to uers. */
        unsigned int msbThreadCfg : 1; /* * [4:4]0:msb thread is used as special thread only used in response
                                    channel;1:msb thread is used as normal thread only used in request channel;*NOTE:
                                    This bit and smeg 1.smeg1_cfg0.msb_thread_cfg should be configure the same value */
        unsigned int memChkEn : 1; /* * [5:5]memory parity check enable.1'b0:disable all memories err check.1'b1:enable
                                    * all memories err check.
                                    */
        unsigned int rpL2nicDbPseudoApiEn : 1; /* * [6:6]L2NIC DB pseudo API enable:1'b1: judge the API TYPE (pseudo or
                                                * not) according to the "pseudo" bit in API;1'b0: All L2NIC DB API is
                                                * regarded as non-pseudo API.
                                                */
        unsigned int reserved1 : 9;            /* * [15:7]reserved */
        unsigned int spRamTmod : 7;      /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                          * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                          */
        unsigned int memRet1n : 1;       /* * [23:23]control of memory pin RET1N */
        unsigned int rpCrtErrInjReq : 1; /* * [24:24]ECC crt err injection requestion;err injection start when posedge
                                      of this bit is detected; After Err injection start, err is injected when a memory
                                      read is issu ed to the memory.Enable memory check, when use this err inection
                                      function. */
        unsigned int rpUncrtErrInjReq : 1; /* * [25:25]ECC uncrt err injection requestion;err injection start when
                                        posedge of this bit is detected; After Err injection start, err is injected when
                                        a memory read is is sued to the memory. Enable memory check, when use this err
                                        inection function. */
        unsigned int reserved0 : 6;        /* * [31:26]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CFG_U;

/* **
* Union name :    SMIR_HASH_SEED0
* @brief               Hash function seed conifg register. This register used to change the original seed of hash
function.

* Description:
*/
typedef union tagUnSmirHashSeed0 {
    struct tagStSmirHashSeed0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int hashSeedCfg0 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the
                                         * original seed[31:0] of hash function.
                                         */
#else
        unsigned int hashSeedCfg0 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the
                                         * original seed[31:0] of hash function.
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_HASH_SEED0_U;

/* **
* Union name :    SMIR_HASH_SEED1
* @brief               Hash function seed conifg register. This register used to change the original seed of hash
function.

* Description:
*/
typedef union tagUnSmirHashSeed1 {
    struct tagStSmirHashSeed1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int hashSeedCfg1 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the
                                         * original seed[63:32] of hash function.
                                         */
#else
        unsigned int hashSeedCfg1 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the
                                         * original seed[63:32] of hash function.
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_HASH_SEED1_U;

/* **
 * Union name :    SMIR_INT_VECTOR
 * @brief
 * Description:
 */
typedef union tagUnSmirIntVector {
    struct tagStSmirIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                     * register0:interrupt disable1:interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24;  /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                    that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                    dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;     /* * [26:24]reserved */
        unsigned int enable : 1;        /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                         * register0:interrupt disable1:interrupt enable
                                         */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_INT_VECTOR_U;

/* **
 * Union name :    SMIR_INT
 * @brief               SMIR interrupt data
 * Description:
 */
typedef union tagUnSmirInt {
    struct tagStSmirInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 11;     /* * [15:5]reserved */
        unsigned int intData : 5;       /* * [4:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 5;   /* * [4:0]interrupt masked field,it is the collection of the error bits from the
                                     * corresponding error registers on the sheet
                                     */
        unsigned int reserved : 11; /* * [15:5]reserved */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_INT_U;

/* **
 * Union name :    SMIR_INT_MASK
 * @brief               SMIR interrupt mask configuration
 * Description:
 */
typedef union tagUnSmirIntMask {
    struct tagStSmirIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 11;     /* * [15:5]reserved */
        unsigned int errMask : 5; /* * [4:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 5; /* * [4:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 11;     /* * [15:5]reserved */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_INT_MASK_U;

/* **
 * Union name :    SMIR_ERR_SPEC_TH
 * @brief               Int[0] :specital thread drop for busy.
 * Description:
 */
typedef union tagUnSmirErrSpecTh {
    struct tagStSmirErrSpecTh {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is
                               off.Capture data format as following:31:25 - thread id;24:19 - src_tag_h;18:14 - src;13:8
                               - in stance ID;7:2   - OP-CODE （include ACK bit） */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is
                                    off.Capture data format as following:31:25 - thread id;24:19 - src_tag_h;18:14 - src;13:8
                                    - in stance ID;7:2   - OP-CODE （include ACK bit） */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_ERR_SPEC_TH_U;

/* **
 * Union name :    SMIR_REQ_MSG_ERR
 * @brief               SMIR request channel message error register.
 * Description:
 */
typedef union tagUnSmirReqMsgErr {
    struct tagStSmirReqMsgErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4
                              Error typeBit0:message with E0-bitbit1:mmessage with E1-bitbit2:message over length
                              bit3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of
                              error message.bit[9:8]   : codebit[15:10] : op_id  （include ACK bit）bit[ 21:16] :
                              instancebit[26:22] : srcBit27~29 RSV */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4
                              Error typeBit0:message with E0-bitbit1:mmessage with E1-bitbit2:message over length
                              bit3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of
                              error message.bit[9:8]   : codebit[15:10] : op_id  （include ACK bit）bit[ 21:16] :
                              instancebit[26:22] : srcBit27~29 RSV */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_REQ_MSG_ERR_U;

/* **
 * Union name :    SMIR_RESP_MSG_ERR
 * @brief               SMIR response channel message error register.
 * Description:
 */
typedef union tagUnSmirRespMsgErr {
    struct tagStSmirRespMsgErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4
                              Error typeBit0:message with E0-bitbit1:message with E1-bitbit2:message over lengthb
                              it3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of
                              error message.bit[9:8]   : codebit[15:10] : op_idbit[21:16] : instancebit [26:22] :
                              srcBit27~29 RSV */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4
                              Error typeBit0:message with E0-bitbit1:message with E1-bitbit2:message over lengthb
                              it3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of
                              error message.bit[9:8]   : codebit[15:10] : op_idbit[21:16] : instancebit [26:22] :
                              srcBit27~29 RSV */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_RESP_MSG_ERR_U;

/* **
 * Union name :    SMIR_MEM_ECC_CRT_ERR
 * @brief               smir memory ecc correctable error
 * Description:
 */
typedef union tagUnSmirMemEccCrtErr {
    struct tagStSmirMemEccCrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                               Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error
                               is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error
                               address;Bit29:16 reserved.
                               */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                               Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error
                               is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error
                               address;Bit29:16 reserved.
                               */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_MEM_ECC_CRT_ERR_U;

/* **
 * Union name :    SMIR_MEM_ECC_UNCRT_ERR
 * @brief               smir memory ecc uncorrectable error
 * Description:
 */
typedef union tagUnSmirMemEccUncrtErr {
    struct tagStSmirMemEccUncrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                               Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error
                               is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error
                               address;Bit29:16 reserved.
                               */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1
                               Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error
                               is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error
                               address;Bit29:16 reserved.
                               */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_MEM_ECC_UNCRT_ERR_U;

/* **
 * Union name :    SMIR_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmirIndrectCtrl {
    struct tagStSmirIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smirIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                     invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                     indirect ac cess valid (software set). */
        unsigned int smirIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smirIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                         * done;2’b01: indirect access timeout;Others: reserved.
                                         */
        unsigned int smirIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: FIPR;4’b0001: RSS hash
                                    memory4' b0010: VAT memory, only in SMF4' b0011: TPT(timer position table), only in
                                    SMFother s:reserved */
        unsigned int smirIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address
                                     in one group or internal address of the table.bit[13:5] memory address in SMF:
                                     FIPR; only bi t8:4 is valid;  RSS_Hash:only bit 7:4 is valid;  VAT: bit 13:4 is
                                     valid TPT: only bit 8:4 is valid in SML mode:  FIPR; only bit9:4 is valid;
                                     RSS_Hash:only bit 7:4 is valid;bit[3:0] word select for RSS MEM:   0~3 reserved,
                                     4:mem_dat[352:321]           // ECC Code, read only for CSR   5:{31bit RSV,
                                     mem_dat[320]}   6: mem_dat[319:288]   7:mem_dat[287:256]   8:mem_dat[255:224]
                                     9:mem_dat[223:192]   10:mem_dat[191:160]   11:mem_dat[159:128]   12:mem_dat[127:96]
                                     13:mem_dat[95 :64]   14:mem_dat[63:32]   15:mem_dat[31:0]bit[3:0] word select for
                                     VAT MEM:   0~11 reserved,   12:{24Bit RSV, mem_data[84:77]}   // ECC Code, read
                                     only for CSR 13:{19Bit RSV, mem_dat[76:64]}   14:mem_dat[63:32]
                                     15:mem_dat[31:0]Note: for accessing FIPR/TPT,bit[3:0] should be 4'hf.
                                      */
#else
        unsigned int smirIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address
                                     in one group or internal address of the table.bit[13:5] memory address in SMF:
                                     FIPR; only bi t8:4 is valid;  RSS_Hash:only bit 7:4 is valid;  VAT: bit 13:4 is
                                     valid TPT: only bit 8:4 is valid in SML mode:  FIPR; only bit9:4 is valid;
                                     RSS_Hash:only bit 7:4 is valid;bit[3:0] word select for RSS MEM:   0~3 reserved,
                                     4:mem_dat[352:321]           // ECC Code, read only for CSR   5:{31bit RSV,
                                     mem_dat[320]}   6: mem_dat[319:288]   7:mem_dat[287:256]   8:mem_dat[255:224]
                                     9:mem_dat[223:192]   10:mem_dat[191:160]   11:mem_dat[159:128]   12:mem_dat[127:96]
                                     13:mem_dat[95 :64]   14:mem_dat[63:32]   15:mem_dat[31:0]bit[3:0] word select for
                                     VAT MEM:   0~11 reserved,   12:{24Bit RSV, mem_data[84:77]}   // ECC Code, read
                                     only for CSR 13:{19Bit RSV, mem_dat[76:64]}   14:mem_dat[63:32]
                                     15:mem_dat[31:0]Note: for accessing FIPR/TPT,bit[3:0] should be 4'hf.
                                      */
        unsigned int smirIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: FIPR;4’b0001: RSS hash
                                    memory4' b0010: VAT memory, only in SMF4' b0011: TPT(timer position table), only in
                                    SMFother s:reserved */
        unsigned int smirIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                         * done;2’b01: indirect access timeout;Others: reserved.
                                         */
        unsigned int smirIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smirIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                     invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                     indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_INDRECT_CTRL_U;

/* **
 * Union name :    SMIR_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmirIndrectTimeout {
    struct tagStSmirIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smirIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smirIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMIR_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmirIndrectData {
    struct tagStSmirIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smirIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#else
        unsigned int smirIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_INDRECT_DATA_U;

/* **
* Union name :    SMIR_CAP0_CFG
* @brief               SMIR capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.(need to enable per field via <cap_sel _en>
in <smir_en_cnt> )
* Description:
*/
typedef union tagUnSmirCap0Cfg {
    struct tagStSmirCap0Cfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not
                               capture any message.1:capture mode enable.smir will compare the selected fields,only the
                               mes sages matched with all selected fields will be captured.Note：field match enable
                               config can be found in SMIR_EN_CNT register.
                                */
        unsigned int sE1Bit : 1; /* * [30:30]E1 field in first flit to capture . It can be enable via <cap_sel_en> field
                               in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users
                               may  get information in Error register. */
        unsigned int sE0Bit : 1; /* * [29:29]E0 field in first flit to capture . It can be enable via <cap_sel_en> field
                               in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users
                               may  get information in Error register. */
        unsigned int sCode : 2;  /* * [28:27]code field to capture . It can be enable via <cap_sel_en> field in register
                                  * <smir_en_cnt> .
                                  */
        unsigned int sOpId : 6;  /* * [26:21]opcode field to capture . It can be enable via <cap_sel_en> field in
                                  * register <smir_en_cnt> .
                                  */
        unsigned int sInstId : 6; /* * [20:15]inst_id field to capture . It can be enable via <cap_sel_en> field in
                                   * register <smir_en_cnt> .
                                   */
        unsigned int src : 5;     /* * [14:10]src field to capture . It can be enable via <cap_sel_en> field in register
                                   * <smir_en_cnt> .
                                   */
        unsigned int reserved : 4; /* * [9:6]reserved */
        unsigned int stagH : 6;    /* * [5:0]src_tag_h field to capture . It can be enable via <cap_sel_en> field in
                                    * register <smir_en_cnt> .
                                    */
#else
        unsigned int stagH : 6;    /* * [5:0]src_tag_h field to capture . It can be enable via <cap_sel_en> field in
                                    * register <smir_en_cnt> .
                                    */
        unsigned int reserved : 4; /* * [9:6]reserved */
        unsigned int src : 5;     /* * [14:10]src field to capture . It can be enable via <cap_sel_en> field in register
                                   * <smir_en_cnt> .
                                   */
        unsigned int sInstId : 6; /* * [20:15]inst_id field to capture . It can be enable via <cap_sel_en> field in
                                   * register <smir_en_cnt> .
                                   */
        unsigned int sOpId : 6;   /* * [26:21]opcode field to capture . It can be enable via <cap_sel_en> field in
                                   * register <smir_en_cnt> .
                                   */
        unsigned int sCode : 2;  /* * [28:27]code field to capture . It can be enable via <cap_sel_en> field in register
                                  * <smir_en_cnt> .
                                  */
        unsigned int sE0Bit : 1; /* * [29:29]E0 field in first flit to capture . It can be enable via <cap_sel_en> field
                               in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users
                               may  get information in Error register. */
        unsigned int sE1Bit : 1; /* * [30:30]E1 field in first flit to capture . It can be enable via <cap_sel_en> field
                               in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users
                               may  get information in Error register. */
        unsigned int capMode : 1;        /* * [31:31]capture mode control register. 0:capture mode disable.smir will not
                                      capture any message.1:capture mode enable.smir will compare the selected fields,only the
                                      mes sages matched with all selected fields will be captured.Note：field match enable
                                      config can be found in SMIR_EN_CNT register.
                                       */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP0_CFG_U;

/* **
* Union name :    SMIR_CAP1_CFG
* @brief               SMIR capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.

* Description:
*/
typedef union tagUnSmirCap1Cfg {
    struct tagStSmirCap1Cfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int flit011196 : 16;    /* * [31:16]flit0 bit111~bit96 field to capture . */
        unsigned int flit011196Msk : 16; /* * [15:0]flit0 bit111~bit96 capture mask. 1:corresponding bit must match when
                                          * capture.0:don't care whether corresponding bit match when capture.
                                          */
#else
        unsigned int flit011196Msk : 16; /* * [15:0]flit0 bit111~bit96 capture mask. 1:corresponding bit must match when
                                          * capture.0:don't care whether corresponding bit match when capture.
                                          */
        unsigned int flit011196 : 16;    /* * [31:16]flit0 bit111~bit96 field to capture . */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP1_CFG_U;

/* **
* Union name :    SMIR_CAP2_CFG
* @brief               SMIR capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.

* Description:
*/
typedef union tagUnSmirCap2Cfg {
    struct tagStSmirCap2Cfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int flit09564 : 32; /* * [31:0]flit0 bit95~bit64 field to capture .  */
#else
        unsigned int flit09564 : 32;     /* * [31:0]flit0 bit95~bit64 field to capture .  */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP2_CFG_U;

/* **
* Union name :    SMIR_CAP3_CFG
* @brief               SMIR capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.

* Description:
*/
typedef union tagUnSmirCap3Cfg {
    struct tagStSmirCap3Cfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int flit06332 : 32; /* * [31:0]flit0 bit63~bit32 field to capture .  */
#else
        unsigned int flit06332 : 32;     /* * [31:0]flit0 bit63~bit32 field to capture .  */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP3_CFG_U;

/* **
* Union name :    SMIR_CAP4_CFG
* @brief               SMIR capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.

* Description:
*/
typedef union tagUnSmirCap4Cfg {
    struct tagStSmirCap4Cfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int flit0310 : 32; /* * [31:0]flit0 bit31~bit0 field to capture .  */
#else
        unsigned int flit0310 : 32;      /* * [31:0]flit0 bit31~bit0 field to capture .  */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP4_CFG_U;

/* **
* Union name :    SMIR_CAP6_CFG
* @brief               SMIR capture fields configuration register .This is used for debug . The software can
configure capture conditions here .For example ,the software want to c apture message and count matched message .The
software can enable <cap_mode> field  and cofigure compare fields data here.

* Description:
*/
typedef union tagUnSmirCap6Cfg {
    struct tagStSmirCap6Cfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 6;    /* * [31:26]reserved */
        unsigned int flit0950Msk : 6; /* * [25:20]flit0 bit95~bit0 capture mask.1 mask bit is corresponding 16bit data.
                                   1:corresponding bit must match when capture.0:don't care whether corresponding bit
                                   match w hen capture.   .  */
        unsigned int capThreadIdEn : 1; /* * [19:19]Condition fields enable according to match fields in registers
                                      <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      outband E bit field in message match according field in message. 0 ,No need to
                                      match this field .This field's capture valid.
                                      */
        unsigned int threadId : 7; /* * [18:12]thread_id field to capture . It can be enable via cap_thread_id_en . */
        unsigned int stagL : 12;   /* * [11:0]src_tag_l field to capture . It can be enable via <cap_sel_en> field in
                                    * register <smir_en_cnt> .
                                    */
#else
        unsigned int stagL : 12;   /* * [11:0]src_tag_l field to capture . It can be enable via <cap_sel_en> field in
                                    * register <smir_en_cnt> .
                                    */
        unsigned int threadId : 7; /* * [18:12]thread_id field to capture . It can be enable via cap_thread_id_en . */
        unsigned int capThreadIdEn : 1; /* * [19:19]Condition fields enable according to match fields in registers
                                      <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                      outband E bit field in message match according field in message. 0 ,No need to
                                      match this field .This field's capture valid.
                                      */
        unsigned int flit0950Msk : 6; /* * [25:20]flit0 bit95~bit0 capture mask.1 mask bit is corresponding 16bit data.
                                   1:corresponding bit must match when capture.0:don't care whether corresponding bit
                                   match w hen capture.   .  */
        unsigned int reserved : 6;    /* * [31:26]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP6_CFG_U;

/* **
* Union name :    SMIR_EN_CNT
* @brief               SMIR mappable event counter controal . The software use this control to configure expected
counter mapping .

* Description:
*/
typedef union tagUnSmirEnCnt {
    struct tagStSmirEnCnt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int capStagLEn : 1; /* * [31:31]Condition fields enable according to match fields in registers
                                  <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                  src_tag_l field in message match according field in message. 0 ,No need to match this
                                  field .This field's capture valid.
                                   */
        unsigned int capErr1En : 1;  /* * [30:30]Condition fields enable according to match fields in registers
                                   <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when outband
                                   E bit field in message match according field in message. 0 ,No need to match this
                                   field .This field's capture valid.
                                   */
        unsigned int capErr0En : 1;  /* * [29:29]Condition fields enable according to match fields in registers
                                   <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when outband
                                   E bit field in message match according field in message. 0 ,No need to match this
                                   field .This field's capture valid.
                                   */
        unsigned int capCodeEn : 1;  /* * [28:28]Condition fields enable according to match fields in registers
                                  <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when outband
                                  code field in message match according field in message. 0 ,No need to match this field
                                  .This field's capture valid.
                                   */
        unsigned int capOpEn : 1;    /* * [27:27]Condition fields enable according to match fields in registers
                                  <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when opcode
                                  field in mes sage match according field in message. 0 ,No need to match this field .This
                                  field's capture valid.
                                   */
        unsigned int capInstEn : 1;  /* * [26:26]Condition fields enable according to match fields in registers
                                  <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when inst_id
                                  field in me ssage match according field in message. 0 ,No need to match this field
                                  .This field's capture valid.
                                   */
        unsigned int capSrcEn : 1;   /* * [25:25]Condition fields enable according to match fields in registers
                                  <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when src field
                                  in messag e match according field in message. 0 ,No need to match this field .This
                                  field's capture valid.
                                   */
        unsigned int capStagHEn : 1; /* * [24:24]Condition fields enable according to match fields in registers
                                  <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when stag
                                  field in messa ge match according field in message. 0 ,No need to match this field
                                  .This field's capture valid.
                                   */
        unsigned int
            smirEnCnt2 : 8; /* * [23:16]Couter source select vector for physical counter2. software can configure this
                         register to decide which counter should be counted into physical counter 2.bit_7: counter
                         enable1'b0:disable counting.1'b1:enable counting.bit_6: channel selection1'b0:this counter will
                         only count the request channel.1'b1:this counter will o nly count the response
                         channel.bit_5:capture Conditional count enable . This is used for debug .When Software
                         enable this field, then only messages matched with  capture condition inside regiser <
                         smir_cap_cfg>  will trigger counting. Otherwise ,counter will be triggerd for all kinds of
                         messages . 1 : count only wh en message match capture trigger condition.0 : count for all
                         messages.bit_4:reserved.bit[3:0]:counter input selection,config one value to choose which type
                         you want count:4'h0:received flits number4'h1:received messages number4'h2:received sop
                         number4'h3:received eop number4'h4:flits sent to smeg14'h5:messages sent to smeg14'h6:flits
                         sent to smeg04'h7:messages sent to smeg04'h8:RSV4'h9:RSV4'ha:RSV4'hb:RSV4'hc:flits dropped by
                         smir4'hd:messages dropped by smir4'he~4'hf:reserve d. */
        unsigned int smirEnCnt1 : 8; /* * [15:8]Counter configure register for SMIR_CNT1; Function is as same as
                                        smir_en_cnt_2 */
        unsigned int smirEnCnt0 : 8; /* * [7:0]Counter configure register for SMIR_CNT0; Function is as same as
                                        smir_en_cnt_2 */
#else
        unsigned int smirEnCnt0 : 8;  /* * [7:0]Counter configure register for SMIR_CNT0; Function is as same as
                                         smir_en_cnt_2 */
        unsigned int smirEnCnt1 : 8;  /* * [15:8]Counter configure register for SMIR_CNT1; Function is as same as
                                         smir_en_cnt_2 */
        unsigned int
            smirEnCnt2 : 8; /* * [23:16]Couter source select vector for physical counter2. software can configure this
                         register to decide which counter should be counted into physical counter 2.bit_7: counter
                         enable1'b0:disable counting.1'b1:enable counting.bit_6: channel selection1'b0:this counter will
                         only count the request channel.1'b1:this counter will o nly count the response
                         channel.bit_5:capture Conditional count enable . This is used for debug .When Software
                         enable this field, then only messages matched with  capture condition inside regiser <
                         smir_cap_cfg>  will trigger counting. Otherwise ,counter will be triggerd for all kinds of
                         messages . 1 : count only wh en message match capture trigger condition.0 : count for all
                         messages.bit_4:reserved.bit[3:0]:counter input selection,config one value to choose which type
                         you want count:4'h0:received flits number4'h1:received messages number4'h2:received sop
                         number4'h3:received eop number4'h4:flits sent to smeg14'h5:messages sent to smeg14'h6:flits
                         sent to smeg04'h7:messages sent to smeg04'h8:RSV4'h9:RSV4'ha:RSV4'hb:RSV4'hc:flits dropped by
                         smir4'hd:messages dropped by smir4'he~4'hf:reserve d. */
        unsigned int capStagHEn : 1;          /* * [24:24]Condition fields enable according to match fields in registers
                                           <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when stag
                                           field in messa ge match according field in message. 0 ,No need to match this field
                                           .This field's capture valid.
                                            */
        unsigned int capSrcEn : 1;            /* * [25:25]Condition fields enable according to match fields in registers
                                           <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when src field
                                           in messag e match according field in message. 0 ,No need to match this field .This
                                           field's capture valid.
                                            */
        unsigned int capInstEn : 1;           /* * [26:26]Condition fields enable according to match fields in registers
                                           <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when inst_id
                                           field in me ssage match according field in message. 0 ,No need to match this field
                                           .This field's capture valid.
                                            */
        unsigned int capOpEn : 1;             /* * [27:27]Condition fields enable according to match fields in registers
                                           <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when opcode
                                           field in mes sage match according field in message. 0 ,No need to match this field .This
                                           field's capture valid.
                                            */
        unsigned int capCodeEn : 1;           /* * [28:28]Condition fields enable according to match fields in registers
                                           <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when outband
                                           code field in message match according field in message. 0 ,No need to match this field
                                           .This field's capture valid.
                                            */
        unsigned int capErr0En : 1;           /* * [29:29]Condition fields enable according to match fields in registers
                                            <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when outband
                                            E bit field in message match according field in message. 0 ,No need to match this
                                            field .This field's capture valid.
                                            */
        unsigned int capErr1En : 1;           /* * [30:30]Condition fields enable according to match fields in registers
                                            <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when outband
                                            E bit field in message match according field in message. 0 ,No need to match this
                                            field .This field's capture valid.
                                            */
        unsigned int capStagLEn : 1;          /* * [31:31]Condition fields enable according to match fields in registers
                                           <smir_cap_cfg> .When software enable <cap_mode> field :  1, Capture only when
                                           src_tag_l field in message match according field in message. 0 ,No need to match this
                                           field .This field's capture valid.
                                            */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_EN_CNT_U;

/* **
* Union name :    SMIR_CNT0
* @brief               SMIR physical counter 0.software can enable which events to be counted into it via field
<smir_en_cnt_0> in register <SMIR_EN_CNT> .

* Description:
*/
typedef union tagUnSmirCnt0 {
    struct tagStSmirCnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smirCnt0 : 32; /* * [31:0] */
#else
        unsigned int smirCnt0 : 32;           /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CNT0_U;

/* **
* Union name :    SMIR_CNT1
* @brief               SMIR physical counter 1.software can enable which events to be counted into it via field
<smir_en_cnt_1> in register <SMIR_EN_CNT> .

* Description:
*/
typedef union tagUnSmirCnt1 {
    struct tagStSmirCnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smirCnt1 : 32; /* * [31:0] */
#else
        unsigned int smirCnt1 : 32;           /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CNT1_U;

/* **
* Union name :    SMIR_CNT2
* @brief               SMIR physical counter 2.software can enable which events to be counted into it via field
<smir_en_cnt_2> in register <SMIR_EN_CNT> .

* Description:
*/
typedef union tagUnSmirCnt2 {
    struct tagStSmirCnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smirCnt2 : 32; /* * [31:0] */
#else
        unsigned int smirCnt2 : 32;           /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CNT2_U;

/* **
 * Union name :    SMIR_CRDT_CNT
 * @brief               SMIR credit counter CTP register
 * Description:
 */
typedef union tagUnSmirCrdtCnt {
    struct tagStSmirCrdtCnt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 18; /* * [31:14]reserved. */
        unsigned int smmcCtp : 5;   /* * [13:9]RSV */
        unsigned int rqstCtp : 3;   /* * [8:6]credit counter CTP registers for EG1 request channel; */
        unsigned int respCtp : 3;   /* * [5:3]credit counter CTP registers for EG1 response channel; */
        unsigned int eg0Ctp : 3;    /* * [2:0]smeg0 credit counter CTP registers for EG0; */
#else
        unsigned int eg0Ctp : 3;              /* * [2:0]smeg0 credit counter CTP registers for EG0; */
        unsigned int respCtp : 3;             /* * [5:3]credit counter CTP registers for EG1 response channel; */
        unsigned int rqstCtp : 3;             /* * [8:6]credit counter CTP registers for EG1 request channel; */
        unsigned int smmcCtp : 5;             /* * [13:9]RSV */
        unsigned int reserved : 18;           /* * [31:14]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CRDT_CNT_U;

/* **
* Union name :    SMIR_CAP_FLIT0_DATA0
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit0Data0 {
    struct tagStSmirCapFlit0Data0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT0_DATA0_U;

/* **
* Union name :    SMIR_CAP_FLIT0_DATA1
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit0Data1 {
    struct tagStSmirCapFlit0Data1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT0_DATA1_U;

/* **
* Union name :    SMIR_CAP_FLIT1_DATA0
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit1Data0 {
    struct tagStSmirCapFlit1Data0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT1_DATA0_U;

/* **
* Union name :    SMIR_CAP_FLIT1_DATA1
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit1Data1 {
    struct tagStSmirCapFlit1Data1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT1_DATA1_U;

/* **
* Union name :    SMIR_CAP_FLIT2_DATA0
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit2Data0 {
    struct tagStSmirCapFlit2Data0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT2_DATA0_U;

/* **
* Union name :    SMIR_CAP_FLIT2_DATA1
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit2Data1 {
    struct tagStSmirCapFlit2Data1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT2_DATA1_U;

/* **
* Union name :    SMIR_CAP_FLIT3_DATA0
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit3Data0 {
    struct tagStSmirCapFlit3Data0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT3_DATA0_U;

/* **
* Union name :    SMIR_CAP_FLIT3_DATA1
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit3Data1 {
    struct tagStSmirCapFlit3Data1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT3_DATA1_U;

/* **
* Union name :    SMIR_CAP_FLIT4_DATA0
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit4Data0 {
    struct tagStSmirCapFlit4Data0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT4_DATA0_U;

/* **
* Union name :    SMIR_CAP_FLIT4_DATA1
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit4Data1 {
    struct tagStSmirCapFlit4Data1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT4_DATA1_U;

/* **
* Union name :    SMIR_CAP_FLIT5_DATA0
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit5Data0 {
    struct tagStSmirCapFlit5Data0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT5_DATA0_U;

/* **
* Union name :    SMIR_CAP_FLIT5_DATA1
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit5Data1 {
    struct tagStSmirCapFlit5Data1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
#else
        unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMIR_CAP_FLIT5_DATA1_U;

/* **
* Union name :    SMIR_CAP_FLIT0_DATA2
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit0Data2 {
    struct tagStSmirCapFlit0Data2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 29;     /* * [31:3]reserved. */
        unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int captureData0 : 2;  /* * [1:0]record the flit[1:0] of capture message. */
#else
        unsigned int captureData0 : 2;        /* * [1:0]record the flit[1:0] of capture message. */
        unsigned int triggerEnable : 1;       /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int reserved : 29;           /* * [31:3]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP_FLIT0_DATA2_U;

/* **
* Union name :    SMIR_CAP_FLIT1_DATA2
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit1Data2 {
    struct tagStSmirCapFlit1Data2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 29;     /* * [31:3]reserved. */
        unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int captureData0 : 2;  /* * [1:0]record the flit[1:0] of capture message. */
#else
        unsigned int captureData0 : 2;        /* * [1:0]record the flit[1:0] of capture message. */
        unsigned int triggerEnable : 1;       /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int reserved : 29;           /* * [31:3]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP_FLIT1_DATA2_U;

/* **
* Union name :    SMIR_CAP_FLIT2_DATA2
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit2Data2 {
    struct tagStSmirCapFlit2Data2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 29;     /* * [31:3]reserved. */
        unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int captureData0 : 2;  /* * [1:0]record the flit[1:0] of capture message. */
#else
        unsigned int captureData0 : 2;        /* * [1:0]record the flit[1:0] of capture message. */
        unsigned int triggerEnable : 1;       /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int reserved : 29;           /* * [31:3]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP_FLIT2_DATA2_U;

/* **
* Union name :    SMIR_CAP_FLIT3_DATA2
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit3Data2 {
    struct tagStSmirCapFlit3Data2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 29;     /* * [31:3]reserved. */
        unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int captureData0 : 2;  /* * [1:0]record the flit[1:0] of capture message. */
#else
        unsigned int captureData0 : 2;        /* * [1:0]record the flit[1:0] of capture message. */
        unsigned int triggerEnable : 1;       /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int reserved : 29;           /* * [31:3]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP_FLIT3_DATA2_U;

/* **
* Union name :    SMIR_CAP_FLIT4_DATA2
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit4Data2 {
    struct tagStSmirCapFlit4Data2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 29;     /* * [31:3]reserved. */
        unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int captureData0 : 2;  /* * [1:0]record the flit[1:0] of capture message. */
#else
        unsigned int captureData0 : 2;        /* * [1:0]record the flit[1:0] of capture message. */
        unsigned int triggerEnable : 1;       /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int reserved : 29;           /* * [31:3]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP_FLIT4_DATA2_U;

/* **
* Union name :    SMIR_CAP_FLIT5_DATA2
* @brief               SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower
127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug .
Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here.

* Description:
*/
typedef union tagUnSmirCapFlit5Data2 {
    struct tagStSmirCapFlit5Data2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 29;     /* * [31:3]reserved. */
        unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int captureData0 : 2;  /* * [1:0]record the flit[1:0] of capture message. */
#else
        unsigned int captureData0 : 2;        /* * [1:0]record the flit[1:0] of capture message. */
        unsigned int triggerEnable : 1;       /* * [2:2]0:trigger is disable1:trigger enable */
        unsigned int reserved : 29;           /* * [31:3]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIR_CAP_FLIT5_DATA2_U;


/* **
 * Union name :    SMEG0_ABUF0_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmeg0Abuf0Version {
    struct tagStSmeg0Abuf0Version {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0Abuf0Version : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smeg0Abuf0Version : 32;  /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_ABUF0_VERSION_U;

/* **
 * Union name :    SM_ABUF_TH_GRW_WM_0
 * @brief               This is the Sm Abuf0 grow watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThGrwWm0 {
    struct tagStSmAbufThGrwWm0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2; /* * [31:30]reserved */
        unsigned int thGrow0 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                               free nodes (free node number/total free node number) is below this threshold.Notice: thi
                               s free node number is equal to the current counter in the list info but not include the
                               free nodes in the prefetch FIFO.Bit[5:0] list0,Bit[11:6] list1,...Bit[29 :24] list4,<The
                               following statement can be changed for clarity.>Eg:For list0, th_grow_0[5:0] can indicate
                               64 grow water-mark thresholds:6'd0: which means grow f lag will never generate.you can
                               say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current
                               free node number in free list is less than 1/64 of total free node number,abuf0 will set
                               grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num
                                */
#else
        unsigned int thGrow0 : 30;   /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                                 free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                 s free node number is equal to the current counter in the list info but not include the
                                 free nodes in the prefetch FIFO.Bit[5:0] list0,Bit[11:6] list1,...Bit[29 :24] list4,<The
                                 following statement can be changed for clarity.>Eg:For list0, th_grow_0[5:0] can indicate
                                 64 grow water-mark thresholds:6'd0: which means grow f lag will never generate.you can
                                 say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current
                                 free node number in free list is less than 1/64 of total free node number,abuf0 will set
                                 grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num
                                  */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_GRW_WM_0_U;

/* **
 * Union name :    SM_ABUF_TH_GRW_WM_1
 * @brief               This is the Sm abuf0 grow watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThGrwWm1 {
    struct tagStSmAbufThGrwWm1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2; /* * [31:30]reserved */
        unsigned int thGrow1 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                               free nodes (free node number/total free node number) is below this threshold.Notice: thi
                               s free node number is equal to the current counter in the list info but not include the
                               free nodes in the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29: 24] list9,<The
                               following statement can be changed for clarity.>Eg:For list5, th_grow_1[5:0] can indicate
                               64 grow water-mark thresholds:6'd0: which means grow fl ag will never generate.you can
                               say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current
                               free node number in free list is less t han 1/64 of total free node number,abuf0 will set
                               grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num
                                */
#else
        unsigned int thGrow1 : 30;   /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                                 free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                 s free node number is equal to the current counter in the list info but not include the
                                 free nodes in the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29: 24] list9,<The
                                 following statement can be changed for clarity.>Eg:For list5, th_grow_1[5:0] can indicate
                                 64 grow water-mark thresholds:6'd0: which means grow fl ag will never generate.you can
                                 say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current
                                 free node number in free list is less t han 1/64 of total free node number,abuf0 will set
                                 grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num
                                  */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_GRW_WM_1_U;

/* **
 * Union name :    SM_ABUF_TH_GRW_WM_2
 * @brief               This is the Sm abuf0 grow watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThGrwWm2 {
    struct tagStSmAbufThGrwWm2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2; /* * [31:30]reserved */
        unsigned int thGrow2 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                               free nodes (free node number/total free node number) is below this threshold.Notice: thi
                               s free node number is equal to the current counter in the list info but not include the
                               free nodes in the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[2 9:24]
                               list14,<The following statement can be changed for clarity.>Eg:For list10, th_grow_2[5:0]
                               can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                               generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                               that if the current free node number in free list is le ss than 1/64 of total free node
                               number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                               63/64*total_num
                                */
#else
        unsigned int thGrow2 : 30;   /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                                 free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                 s free node number is equal to the current counter in the list info but not include the
                                 free nodes in the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[2 9:24]
                                 list14,<The following statement can be changed for clarity.>Eg:For list10, th_grow_2[5:0]
                                 can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                                 generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                                 that if the current free node number in free list is le ss than 1/64 of total free node
                                 number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                                 63/64*total_num
                                  */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_GRW_WM_2_U;

/* **
 * Union name :    SM_ABUF_TH_GRW_WM_3
 * @brief               This is the Sm abuf0 grow watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThGrwWm3 {
    struct tagStSmAbufThGrwWm3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2; /* * [31:30]reserved */
        unsigned int thGrow3 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                               free nodes (free node number/total free node number) is below this threshold.Notice: thi
                               s free node number is equal to the current counter in the list info but not include the
                               free nodes in the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[2 9:24]
                               list19,<The following statement can be changed for clarity.>Eg:For list15, th_grow_3[5:0]
                               can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                               generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                               that if the current free node number in free list is le ss than 1/64 of total free node
                               number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                               63/64*total_num
                                */
#else
        unsigned int thGrow3 : 30;   /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                                 free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                 s free node number is equal to the current counter in the list info but not include the
                                 free nodes in the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[2 9:24]
                                 list19,<The following statement can be changed for clarity.>Eg:For list15, th_grow_3[5:0]
                                 can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                                 generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                                 that if the current free node number in free list is le ss than 1/64 of total free node
                                 number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                                 63/64*total_num
                                  */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_GRW_WM_3_U;

/* **
 * Union name :    SM_ABUF_TH_GRW_WM_4
 * @brief               This is the Sm abuf0 grow watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThGrwWm4 {
    struct tagStSmAbufThGrwWm4 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2; /* * [31:30]reserved */
        unsigned int thGrow4 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                               free nodes (free node number/total free node number) is below this threshold.Notice: thi
                               s free node number is equal to the current counter in the list info but not include the
                               free nodes in the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[2 9:24]
                               list24,<The following statement can be changed for clarity.>Eg:For list20, th_grow_4[5:0]
                               can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                               generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                               that if the current free node number in free list is le ss than 1/64 of total free node
                               number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                               63/64*total_num
                                */
#else
        unsigned int thGrow4 : 30;   /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                                 free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                 s free node number is equal to the current counter in the list info but not include the
                                 free nodes in the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[2 9:24]
                                 list24,<The following statement can be changed for clarity.>Eg:For list20, th_grow_4[5:0]
                                 can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                                 generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                                 that if the current free node number in free list is le ss than 1/64 of total free node
                                 number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                                 63/64*total_num
                                  */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_GRW_WM_4_U;

/* **
 * Union name :    SM_ABUF_TH_GRW_WM_5
 * @brief               This is the Sm abuf0 grow watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThGrwWm5 {
    struct tagStSmAbufThGrwWm5 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2; /* * [31:30]reserved */
        unsigned int thGrow5 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                               free nodes (free node number/total free node number) is below this threshold.Notice: thi
                               s free node number is equal to the current counter in the list info but not include the
                               free nodes in the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[2 9:24]
                               list29,<The following statement can be changed for clarity.>Eg:For list25, th_grow_4[5:0]
                               can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                               generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                               that if the current free node number in free list is le ss than 1/64 of total free node
                               number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                               63/64*total_num
                                */
#else
        unsigned int thGrow5 : 30;   /* * [29:0]Hardware will inform the software to grow when the actual percentage of
                                 free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                 s free node number is equal to the current counter in the list info but not include the
                                 free nodes in the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[2 9:24]
                                 list29,<The following statement can be changed for clarity.>Eg:For list25, th_grow_4[5:0]
                                 can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never
                                 generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means
                                 that if the current free node number in free list is le ss than 1/64 of total free node
                                 number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63:
                                 63/64*total_num
                                  */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_GRW_WM_5_U;

/* **
 * Union name :    SM_ABUF_TH_GRW_WM_6
 * @brief               This is the Sm abuf0 grow watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThGrwWm6 {
    struct tagStSmAbufThGrwWm6 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 20; /* * [31:12]reserved */
        unsigned int thGrow6 : 12;  /* * [11:0]Hardware will inform the software to grow when the actual percentage of
                                free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                s free node number is equal to the current counter in the list info but not include the
                                free nodes in the prefetch FIFOBit[5:0] list30,Bit[11:6] list31<The foll owing statement
                                can be changed for clarity.>Eg:For list30, th_grow_5[5:0] can indicate 64 grow water-mark
                                thresholds:6'd0: which means grow flag will never gene rate.you can say Disable grow
                                water-mark generate.6'd1: 1/64*total_num,which means that if the current free node number
                                in free list is less than 1/64 of total free node number,abuf0 will set grow flag and
                                sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num
                                 */
#else
        unsigned int thGrow6 : 12;   /* * [11:0]Hardware will inform the software to grow when the actual percentage of
                                 free nodes (free node number/total free node number) is below this threshold.Notice: thi
                                 s free node number is equal to the current counter in the list info but not include the
                                 free nodes in the prefetch FIFOBit[5:0] list30,Bit[11:6] list31<The foll owing statement
                                 can be changed for clarity.>Eg:For list30, th_grow_5[5:0] can indicate 64 grow water-mark
                                 thresholds:6'd0: which means grow flag will never gene rate.you can say Disable grow
                                 water-mark generate.6'd1: 1/64*total_num,which means that if the current free node number
                                 in free list is less than 1/64 of total free node number,abuf0 will set grow flag and
                                 sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num
                                  */
        unsigned int reserved : 20;  /* * [31:12]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_GRW_WM_6_U;

/* **
 * Union name :    SM_ABUF_TH_SHK_WM_0
 * @brief               This is the Sm abuf0 shrink watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThShkWm0 {
    struct tagStSmAbufThShkWm0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;   /* * [31:30]reserved */
        unsigned int thShrink0 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list0,Bit[11:6] list1,...Bit[29:24] list4,Eg:Fo r list0,
                                 th_shrink_0[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-mark g enerate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
#else
        unsigned int thShrink0 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list0,Bit[11:6] list1,...Bit[29:24] list4,Eg:Fo r list0,
                                 th_shrink_0[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-mark g enerate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_SHK_WM_0_U;

/* **
 * Union name :    SM_ABUF_TH_SHK_WM_1
 * @brief               This is the Sm abuf0 shrink watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThShkWm1 {
    struct tagStSmAbufThShkWm1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;   /* * [31:30]reserved */
        unsigned int thShrink1 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29:24] list9,Eg:Fo r list5,
                                 th_shrink_1[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-mark g enerate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
#else
        unsigned int thShrink1 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29:24] list9,Eg:Fo r list5,
                                 th_shrink_1[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-mark g enerate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_SHK_WM_1_U;

/* **
 * Union name :    SM_ABUF_TH_SHK_WM_2
 * @brief               This is the Sm abuf0 shrink watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThShkWm2 {
    struct tagStSmAbufThShkWm2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;   /* * [31:30]reserved */
        unsigned int thShrink2 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[29:24] list14,Eg :For list10,
                                 th_shrink_2[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
#else
        unsigned int thShrink2 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[29:24] list14,Eg :For list10,
                                 th_shrink_2[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
        unsigned int reserved : 2;   /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_SHK_WM_2_U;

/* **
 * Union name :    SM_ABUF_TH_SHK_WM_3
 * @brief               This is the Sm abuf0 shrink watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThShkWm3 {
    struct tagStSmAbufThShkWm3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;   /* * [31:30]Reserved */
        unsigned int thShrink3 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[29:24] list19,Eg :For list15,
                                 th_shrink_3[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
#else
        unsigned int thShrink3 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[29:24] list19,Eg :For list15,
                                 th_shrink_3[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
        unsigned int reserved : 2;   /* * [31:30]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_SHK_WM_3_U;

/* **
 * Union name :    SM_ABUF_TH_SHK_WM_4
 * @brief               This is the Sm abuf0 shrink watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThShkWm4 {
    struct tagStSmAbufThShkWm4 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;   /* * [31:30]Reserved */
        unsigned int thShrink4 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[29:24] list24,Eg :For list20,
                                 th_shrink_4[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
#else
        unsigned int thShrink4 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[29:24] list24,Eg :For list20,
                                 th_shrink_4[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
        unsigned int reserved : 2;   /* * [31:30]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_SHK_WM_4_U;

/* **
 * Union name :    SM_ABUF_TH_SHK_WM_5
 * @brief               This is the Sm abuf0 shrink watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThShkWm5 {
    struct tagStSmAbufThShkWm5 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;   /* * [31:30]Reserved */
        unsigned int thShrink5 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[29:24] list29,Eg :For list25,
                                 th_shrink_5[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
#else
        unsigned int thShrink5 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[29:24] list29,Eg :For list25,
                                 th_shrink_5[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink
                                 flag will never generate.you can say Disable shrink water-ma rk generate.6'd1:
                                 1/64*total_num,which means that if the current free node number in free list is larger
                                 than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1.
                                 6'd2: 2/64*total_num…6'd63: 63/64*total_num */
        unsigned int reserved : 2;   /* * [31:30]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_SHK_WM_5_U;

/* **
 * Union name :    SM_ABUF_TH_SHK_WM_6
 * @brief               This is the Sm abuf0 shrink watermark config register.
 * Description:
 */
typedef union tagUnSmAbufThShkWm6 {
    struct tagStSmAbufThShkWm6 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 20;  /* * [31:12]Reserved */
        unsigned int thShrink6 : 12; /* * [11:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list30,Bit[11:6] list31Eg:For list30, th_shrink _6[5:0] can
                                 indicate 64 shrink water-mark thresholds:6'd0: which means shrink flag will never
                                 generate.you can say Disable shrink water-mark generate.6'd1: 1/64 *total_num,which
                                 means that if the current free node number in free list is larger than 1/64 of total
                                 free node number,abuf0 will set shrink flag and sent it to smeg1. 6'd2:
                                 2/64*total_num…6'd63: 63/64*total_num */
#else
        unsigned int thShrink6 : 12; /* * [11:0]Hw will indicate software to shrink when actual free nodes percent(free
                                 node number/total free node number) is upper this threshold.Notice: this free node num
                                 ber is equal to the current counter in the list info but not include the free nodes in
                                 the prefetch FIFOBit[5:0] list30,Bit[11:6] list31Eg:For list30, th_shrink _6[5:0] can
                                 indicate 64 shrink water-mark thresholds:6'd0: which means shrink flag will never
                                 generate.you can say Disable shrink water-mark generate.6'd1: 1/64 *total_num,which
                                 means that if the current free node number in free list is larger than 1/64 of total
                                 free node number,abuf0 will set shrink flag and sent it to smeg1. 6'd2:
                                 2/64*total_num…6'd63: 63/64*total_num */
        unsigned int reserved : 20;  /* * [31:12]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_TH_SHK_WM_6_U;

/* **
* Union name :    SM_ABUF_FLRC_ATTR
* @brief               This is the free list reclaim attribute config register.This is used to set up the reclaim
operation on one free list.

* Description:
*/
typedef union tagUnSmAbufFlrcAttr {
    struct tagStSmAbufFlrcAttr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 22; /* * [31:10]reserved */
        unsigned int stopRclm : 1;  /* * [9:9]If sw wants pause or stop reclaim operation while reclaim is running,setup
                                     * this bit.1'b0:cancel stop reclaim.1'b1:stop reclaim.
                                     */
        unsigned int enRclm : 1;    /* * [8:8]reclaim start control bit.Sw can setup this bit after configuring upper
                                 boundary,lower boundary,free list id to be reclaim and reclaim fn number.1'b0: reclaim d
                                 isable;1'b1: reclaim enable. */
        unsigned int reserved1 : 3; /* * [7:5]reserved */
        unsigned int flidTorc : 5;  /* * [4:0]Free list to be reclaimed (free list 1~31). */
#else
        unsigned int flidTorc : 5;   /* * [4:0]Free list to be reclaimed (free list 1~31). */
        unsigned int reserved1 : 3;  /* * [7:5]reserved */
        unsigned int enRclm : 1;     /* * [8:8]reclaim start control bit.Sw can setup this bit after configuring upper
                                  boundary,lower boundary,free list id to be reclaim and reclaim fn number.1'b0: reclaim d
                                  isable;1'b1: reclaim enable. */
        unsigned int stopRclm : 1; /* * [9:9]If sw wants pause or stop reclaim operation while reclaim is running,setup
                                    * this bit.1'b0:cancel stop reclaim.1'b1:stop reclaim.
                                    */
        unsigned int reserved0 : 22;        /* * [31:10]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FLRC_ATTR_U;

/* **
* Union name :    SM_ABUF_FLRC_NUM
* @brief               This is the Sm abuf0 free list reclaim number config register.This is used to set the total
number of free nodes that the software wants to get from the particu lar free list.This register must be set before the
reclaim operation is set up.
* Description:
*/
typedef union tagUnSmAbufFlrcNum {
    struct tagStSmAbufFlrcNum {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 4; /* * [31:28]Reserved */
        unsigned int numRclm : 28; /* * [27:0]Total number of free nodes to be reclaimed. */
#else
        unsigned int numRclm : 28;          /* * [27:0]Total number of free nodes to be reclaimed. */
        unsigned int reserved : 4;          /* * [31:28]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FLRC_NUM_U;

/* **
* Union name :    SM_ABUF_FLRC_BOUND_U
* @brief               This is the Sm abuf0 reclaim upper boundary config register.This is used to set the upper
boundary of the reclaim region.

* Description:
*/
typedef union tagUnSmAbufFlrcBoundU {
    struct tagStSmAbufFlrcBoundU {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufFlrcBoundU : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper
                                        free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id
                                        <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */
#else
        unsigned int smAbufFlrcBoundU : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper
                                        free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id
                                        <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FLRC_BOUND_U_U;

/* **
* Union name :    SM_ABUF_FLRC_BOUND_L
* @brief               Sm abuf0 reclaim lower boundary config register. This register is used to set the lower boundary
of the reclaim region.

* Description:
*/
typedef union tagUnSmAbufFlrcBoundL {
    struct tagStSmAbufFlrcBoundL {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufFlrcBoundL : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper
                                        free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id
                                        <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */
#else
        unsigned int smAbufFlrcBoundL : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper
                                        free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id
                                        <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FLRC_BOUND_L_U;

/* **
* Union name :    SM_ABUF_PF_LIFO_CLR
* @brief               This is the Sm abuf0 pre-fetch lifo clear register.This is used to clear any pfetch lifos if
software wants.(here lifo means Last in first out)

* Description:
*/
typedef union tagUnSmAbufPfLifoClr {
    struct tagStSmAbufPfLifoClr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufPfLifoClr : 32; /* * [31:0]Pre-fetch lifo clear register.Bit[0]:pre-fetch lifo of list
                                       0,Bit[1]:pre-fetch lifo of list 1,….Bit[31]:pre-fetch lifo of list 31,Single bit
                                       description:1'b0:no rmal status,not clear the lifo.1'b1:clear status,clear the
                                       lifo.Note:  User must config the register to normal status if he wants regarding
                                       list work as normal. */
#else
        unsigned int smAbufPfLifoClr : 32;  /* * [31:0]Pre-fetch lifo clear register.Bit[0]:pre-fetch lifo of list
                                        0,Bit[1]:pre-fetch lifo of list 1,….Bit[31]:pre-fetch lifo of list 31,Single bit
                                        description:1'b0:no rmal status,not clear the lifo.1'b1:clear status,clear the
                                        lifo.Note:  User must config the register to normal status if he wants regarding
                                        list work as normal. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_PF_LIFO_CLR_U;

/* **
 * Union name :    SM_ABUF_MEM_CFG
 * @brief               This is the Sm abuf0 parity bit check enable config register.
 * Description:
 */
typedef union tagUnSmAbufMemCfg {
    struct tagStSmAbufMemCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 8; /* * [31:24]reserved */
        unsigned int tpRamTmod : 8; /* * [23:16]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                     * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                     */
        unsigned int memRet1n : 1;  /* * [15:15]control of memory pin RET1N */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int reserved1 : 3; /* * [7:5]reserved */
        unsigned int pbChkEn : 1;   /* * [4:4]reserved */
        unsigned int ireqPberrGen : 1; /* * [3:3]reserved */
        unsigned int ibufPberrGen : 1; /* * [2:2]reserved */
        unsigned int infoPberrGen : 1; /* * [1:1]reserved */
        unsigned int lifoPberrGen : 1; /* * [0:0]reserved */
#else
        unsigned int lifoPberrGen : 1;      /* * [0:0]reserved */
        unsigned int infoPberrGen : 1;      /* * [1:1]reserved */
        unsigned int ibufPberrGen : 1;      /* * [2:2]reserved */
        unsigned int ireqPberrGen : 1;      /* * [3:3]reserved */
        unsigned int pbChkEn : 1;           /* * [4:4]reserved */
        unsigned int reserved1 : 3;         /* * [7:5]reserved */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int memRet1n : 1;  /* * [15:15]control of memory pin RET1N */
        unsigned int tpRamTmod : 8; /* * [23:16]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                     * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                     */
        unsigned int reserved0 : 8; /* * [31:24]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_MEM_CFG_U;

/* **
* Union name :    SM_ABUF_INT_VECTOR
* @brief               This is the Smart Memory (SM) abuf0 interrupt vector  register.This is used to determine the CP
interrupt address, disable and enable an interrupt report,and pr ovide the  total status of an abuf0 interrupt.
* Description:
*/
typedef union tagUnSmAbufIntVector {
    struct tagStSmAbufIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]Reserved */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:  No interrupt issued;1:  Interrupt issued; CP
                                     * needs to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag that enables all interrupts reported through  this
                                     * register.  0:  Interrupt disable1:  Interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag that enables all interrupts reported through  this
                                     * register.  0:  Interrupt disable1:  Interrupt enable
                                     */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:  No interrupt issued;1:  Interrupt issued; CP
                                     * needs to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_INT_VECTOR_U;

/* **
* Union name :    SM_ABUF_INT
* @brief               This is the SM abuf0 interrupt data register.This is used to record the history of the interrupt
status since the last clear operation. Software can use this re gister to let the CP know, which CSR module, or group of
CSR modules, requested the interrupt.

* Description:
*/
typedef union tagUnSmAbufInt {
    struct tagStSmAbufInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID that indicates to the CP, which CSR module, or
                                    group of CSR modules, asked for the interrupt.Eg:Config program_csr_id=8h3,if sw
                                    access the c sr_node whose csr_id=8'h3,the csr_node is in abuf0.it is the member
                                    description,so it is not neccessary to move it.
                                     */
        unsigned int reserved : 10;     /* * [15:6]reserved */
        unsigned int intData : 6; /* * [5:0]Interrupt masked field.  It is a  collection of the error bits from the
                                   * corresponding error registers on the sheet.
                                   */
#else
        unsigned int intData : 6;   /* * [5:0]Interrupt masked field.  It is a  collection of the error bits from the
                                     * corresponding error registers on the sheet.
                                     */
        unsigned int reserved : 10; /* * [15:6]reserved */
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID that indicates to the CP, which CSR module, or
                                    group of CSR modules, asked for the interrupt.Eg:Config program_csr_id=8h3,if sw
                                    access the c sr_node whose csr_id=8'h3,the csr_node is in abuf0.it is the member
                                    description,so it is not neccessary to move it.
                                     */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_INT_U;

/* **
* Union name :    SM_ABUF_INT_MASK
* @brief               This is the SM abuf0 interrupt mask register.This is used to mask the bits of the interrupt
register that should not be reported to an upper level.Software can use this register to mask corresponding bits if they
do not want those bits reporting to an upper level.

* Description:
*/
typedef union tagUnSmAbufIntMask {
    struct tagStSmAbufIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 10;     /* * [15:6]reserved */
        unsigned int errMask : 6; /* * [5:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 6; /* * [5:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 10;     /* * [15:6]reserved */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_INT_MASK_U;

/* **
* Union name :    SM_ABUF_PBERR
* @brief               This is the ireq_list's output data Parity Bit Error interrupt register.Software can get related
ireq_list information from this register. This register is used for debug.
* Description:
*/
typedef union tagUnSmAbufPberr {
    struct tagStSmAbufPberr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures ireq_list parity error state of the first error capture
                              even if the mask is off.Sticky[0]:ireq_list parity bit error;Sticky[1]:ireq_buf parit y
                              bit error;Sticky[3:2]:ReservedSticky[9:4]:  address of ireq_list has parity
                              error.Sticky[15:10]: which address of ireq_buf has parity error.Sticky[29:16]: Res erved
                              When error_bit or multi_error_bit is set,software can use this register's member to record
                              the  address that has the parity error.
                               */
        unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */
        unsigned int errorBit : 1;      /* * [0:0]0: No error found.  1: Error found. */
#else
        unsigned int errorBit : 1;      /* * [0:0]0: No error found.  1: Error found. */
        unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */
        unsigned int sticky : 30;  /* * [31:2]Abuf0 csr captures ireq_list parity error state of the first error capture
                               even if the mask is off.Sticky[0]:ireq_list parity bit error;Sticky[1]:ireq_buf parit y
                               bit error;Sticky[3:2]:ReservedSticky[9:4]:  address of ireq_list has parity
                               error.Sticky[15:10]: which address of ireq_buf has parity error.Sticky[29:16]: Res erved
                               When error_bit or multi_error_bit is set,software can use this register's member to record
                               the  address that has the parity error.
                                */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_PBERR_U;

/* **
* Union name :    SM_ABUF_FL_UFLOW_ERR
* @brief               This is the free list underflow error interrupt register.This register is used to record the
underflow status of 32 free lists.Any free lists are in underflow s tatus,this register will trigger.This register is
used for debug.  Software can use this register to scan the status of 32 free lists.

* Description:
*/
typedef union tagUnSmAbufFlUflowErr {
    struct tagStSmAbufFlUflowErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error, capture even if mask
                              is off. Sticky[4:0]: The list ID that was in an underflow state.Stick[29]:0-underflo w
                              because get from uneable dis-allocate list          1-underflow because get from empty
                              list;Sticky[28:5]:  Reserved.When the error_bit or even the multi_error _bit is
                              set,software can use this member of the register to record the list ID.  For example, when
                              list 0 is empty, an allocate request will load list0 to be un derflow. */
        unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0: No error founded1: Error founded */
#else
        unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error, capture even if mask
                              is off. Sticky[4:0]: The list ID that was in an underflow state.Stick[29]:0-underflo w
                              because get from uneable dis-allocate list          1-underflow because get from empty
                              list;Sticky[28:5]:  Reserved.When the error_bit or even the multi_error _bit is
                              set,software can use this member of the register to record the list ID.  For example, when
                              list 0 is empty, an allocate request will load list0 to be un derflow. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FL_UFLOW_ERR_U;

/* **
* Union name :    SM_ABUF_FL_OFLOW_ERR
* @brief               This is the free list overflow error interrupt register.This register is used to record the
overflow status of 32 free lists.If any free lists are in an  overfl ow state,this register will trigger.This register
is used for debug.  Software can use this register to scan the status of the 32 free lists.

* Description:
*/
typedef union tagUnSmAbufFlOflowErr {
    struct tagStSmAbufFlOflowErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error.  It captures this
                              even if the mask is off.Sticky[4:0]: The list ID that was in an overflow state.Stick[2
                              9]:0-overflow because put into unenable allocate list          1-overflow because put into
                              a full list;Sticky[28:5]:  Reserved.While the error_bit or even the m ulti_error_bit is
                              set,software can use this member of the register to record corresponding list ID.  For
                              example, when list0 is full,an de-allocate request will load list0 to be overflow. */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;  /* * [31:2]Abuf0 csr captures the error state of the first error.  It captures this
                               even if the mask is off.Sticky[4:0]: The list ID that was in an overflow state.Stick[2
                               9]:0-overflow because put into unenable allocate list          1-overflow because put into
                               a full list;Sticky[28:5]:  Reserved.While the error_bit or even the m ulti_error_bit is
                               set,software can use this member of the register to record corresponding list ID.  For
                               example, when list0 is full,an de-allocate request will load list0 to be overflow. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FL_OFLOW_ERR_U;

/* **
* Union name :    SM_ABUF_FL_TAIL_MISS_ERR
* @brief               This is the tail missed error interrupt register.This is used to capture information of regarding
list whose tail pointer is not equal to the last pointer of th e link list,when the free node group(including the last
pointer) is load from outside DDR.This register is used for debug.

* Description:
*/
typedef union tagUnSmAbufFlTailMissErr {
    struct tagStSmAbufFlTailMissErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures error state of the first error, capture even if mask is
                               off.Sticky[4:0]:the list id that was tail missed.Sticky[29:5] reserve.While error_bit or
                               even multi_error_bit was set,software can use this member of the register to record
                               corresponding list id. If error_bit or multi_error_bit is set,that means the free
                               list(sticy[4:0]) has been destroyed. */
        unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0: No error founded1: Error founded */
#else
        unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures error state of the first error, capture even if mask is
                               off.Sticky[4:0]:the list id that was tail missed.Sticky[29:5] reserve.While error_bit or
                               even multi_error_bit was set,software can use this member of the register to record
                               corresponding list id. If error_bit or multi_error_bit is set,that means the free
                               list(sticy[4:0]) has been destroyed. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FL_TAIL_MISS_ERR_U;

/* **
 * Union name :    SMEG0_ABUF_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmeg0AbufIndrectCtrl {
    struct tagStSmeg0AbufIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0AbufIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect
                                          access invalid, including operation done and timeout (initial value or logic
                                          clear);1’b1: indirect ac cess valid (software set). */
        unsigned int smeg0AbufIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read.
                                              */
        unsigned int smeg0AbufIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                              * done;2’b01: indirect access timeout;Others: reserved.
                                              */
        unsigned int smeg0AbufIndirTab : 4;  /* * [27:24]It specifies memory group or table. 0x0:ireq list0x1:ireq
                                              * buffer0x2:list info0x3:pfetch lifoothers:reserved
                                              */
        unsigned int
            smeg0AbufIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in
                                 one group or internal address of the table.Bit[9:2]memory block read/write
                                 address.differe nt memory block has different address depth and data width. User should
                                 operate on valid address.For SML:Mem_sel Mem_addr 2'b00    0~15   2'b01    0~152'b10
                                 0~31   (DATA) 32~63  (ECC)2'b11    0~127  (DATA)         128~255(ECC)For SMF:Mem_sel
                                 Mem_addr 2'b00 0~31   2'b01    0~312'b10    0~31   (DATA, Read a nd Write) 32~63  (ECC,
                                 read only)2'b11    0~127  (DATA, read and write)         128~255(ECC read
                                 only)-----------------------------bit[1:0]Memory entry Index.Access order:big endian
                                 which LSB accessed by higher address.For ireq list access,0x0~0x2:reserved.0x3:
                                 data[31:0]For ireq_buf access,the memory data widt h of ireq_buf is 38 bit.each entry
                                 index can only access 32bit data. so user should access ireq_buf twice to get 38bit
                                 data.the entry index should be:0x0~0x1:re served.0x2: data[37:32]0x3: data[31:0]For
                                 list info and prefetch lifo,the memory width is 128 bits.each entry index can only
                                 access 32bit data.so user should ac cess list info a four times to get 128 bit
                                 data.0x0:data[127:96]0x1:data[95:64]0x2:data[63:32]0x3:data[31:0] 0x0: {25'd0,ECC[6:0]}
                                 for data[127:96]0x1: {25'd0,E CC[6:0]} for data[95:64]0x2: {25'd0,ECC[6:0]} for
                                 data[63:32]0x3: {25'd0,ECC[6:0]} for data[31:0]BTW: prefetch does not support dynamic
                                 write and if S/W want to
                                  write continous 128 bit, its write address[1:0] must guarantee from 0x3 to 0x0. */
#else
        unsigned int
            smeg0AbufIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in
                                 one group or internal address of the table.Bit[9:2]memory block read/write
                                 address.differe nt memory block has different address depth and data width. User should
                                 operate on valid address.For SML:Mem_sel Mem_addr 2'b00    0~15   2'b01    0~152'b10
                                 0~31   (DATA) 32~63  (ECC)2'b11    0~127  (DATA)         128~255(ECC)For SMF:Mem_sel
                                 Mem_addr 2'b00 0~31   2'b01    0~312'b10    0~31   (DATA, Read a nd Write) 32~63  (ECC,
                                 read only)2'b11    0~127  (DATA, read and write)         128~255(ECC read
                                 only)-----------------------------bit[1:0]Memory entry Index.Access order:big endian
                                 which LSB accessed by higher address.For ireq list access,0x0~0x2:reserved.0x3:
                                 data[31:0]For ireq_buf access,the memory data widt h of ireq_buf is 38 bit.each entry
                                 index can only access 32bit data. so user should access ireq_buf twice to get 38bit
                                 data.the entry index should be:0x0~0x1:re served.0x2: data[37:32]0x3: data[31:0]For
                                 list info and prefetch lifo,the memory width is 128 bits.each entry index can only
                                 access 32bit data.so user should ac cess list info a four times to get 128 bit
                                 data.0x0:data[127:96]0x1:data[95:64]0x2:data[63:32]0x3:data[31:0] 0x0: {25'd0,ECC[6:0]}
                                 for data[127:96]0x1: {25'd0,E CC[6:0]} for data[95:64]0x2: {25'd0,ECC[6:0]} for
                                 data[63:32]0x3: {25'd0,ECC[6:0]} for data[31:0]BTW: prefetch does not support dynamic
                                 write and if S/W want to
                                  write continous 128 bit, its write address[1:0] must guarantee from 0x3 to 0x0. */
        unsigned int smeg0AbufIndirTab : 4;  /* * [27:24]It specifies memory group or table. 0x0:ireq list0x1:ireq
                                              * buffer0x2:list info0x3:pfetch lifoothers:reserved
                                              */
        unsigned int smeg0AbufIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                              * done;2’b01: indirect access timeout;Others: reserved.
                                              */
        unsigned int smeg0AbufIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read.
                                              */
        unsigned int smeg0AbufIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect
                                          access invalid, including operation done and timeout (initial value or logic
                                          clear);1’b1: indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_ABUF_INDRECT_CTRL_U;

/* **
 * Union name :    SMEG0_ABUF_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmeg0AbufIndrectTimeout {
    struct tagStSmeg0AbufIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0AbufIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smeg0AbufIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_ABUF_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMEG0_ABUF_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmeg0AbufIndrectData {
    struct tagStSmeg0AbufIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int
            smeg0AbufIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                 write data to these registes and then enable indirect access, logic will send these
                                 data to target.When operation read:  Logic write data to these registers and refresh
                                 xxx_indir_stat, software will get these data from target.ireq list:bit[7] :even pa rity
                                 check bit of bit[6:0]bit[6:0]: dataireq buffer:bit[37]:even parity check bit of
                                 bit[36:32]bit[31]:even parity check bit of bit[31:0]bit[36:32],bit[30:0]: d atalist
                                 info:bit[31],bit[63],bit[95],bit[127] : even parity check bits of
                                 bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bit[126:96
                                 ] : data.pfetch lifo:bit[31],bit[63],bit[95],bit[127] : even parity check bits of
                                 bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bi
                                 t[126:96] : data. */
#else
        unsigned int
            smeg0AbufIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                 write data to these registes and then enable indirect access, logic will send these
                                 data to target.When operation read:  Logic write data to these registers and refresh
                                 xxx_indir_stat, software will get these data from target.ireq list:bit[7] :even pa rity
                                 check bit of bit[6:0]bit[6:0]: dataireq buffer:bit[37]:even parity check bit of
                                 bit[36:32]bit[31]:even parity check bit of bit[31:0]bit[36:32],bit[30:0]: d atalist
                                 info:bit[31],bit[63],bit[95],bit[127] : even parity check bits of
                                 bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bit[126:96
                                 ] : data.pfetch lifo:bit[31],bit[63],bit[95],bit[127] : even parity check bits of
                                 bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bi
                                 t[126:96] : data. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_ABUF_INDRECT_DATA_U;

/* **
* Union name :    SM_ABUF_DIS_ALLOC
* @brief               This is the SM Abuf0 disable allocation config register.This is used by software to disable the
allocate operation if you do not want to release any free nodes from the particular list.
* Description:
*/
typedef union tagUnSmAbufDisAlloc {
    struct tagStSmAbufDisAlloc {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufDisAlloc : 32; /* * [31:0]SM Application Buffer's disable allocation.1'b0: Enable,1'b1:
                                           * Disable.Bit[0] free list 0,Bit[1] free list 1,Bit[2] free list 2,...Bit[31]
                                           * free list 31.
                                           */
#else
        unsigned int smAbufDisAlloc : 32;   /* * [31:0]SM Application Buffer's disable allocation.1'b0: Enable,1'b1:
                                             * Disable.Bit[0] free list 0,Bit[1] free list 1,Bit[2] free list 2,...Bit[31]
                                             * free list 31.
                                             */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_DIS_ALLOC_U;

/* **
* Union name :    SM_ABUF_DIS_DE_ALLOC
* @brief               This is the SM Abuf0 de_allocate disable config register.This is used by software to disable the
de-allocate operation if you do not want to put any free nodes to the particular  list.
* Description:
*/
typedef union tagUnSmAbufDisDeAlloc {
    struct tagStSmAbufDisDeAlloc {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufDisDeAlloc : 32; /* * [31:0]SM Application Buffer's disable
                                             * de-allocation.1'b0:enable,1'b1:disable.Bit[0] free list 0,Bit[1] free
                                             * list 1,Bit[2] free list 2,...Bit[31] free list 31.
                                             */
#else
        unsigned int smAbufDisDeAlloc : 32; /* * [31:0]SM Application Buffer's disable
                                             * de-allocation.1'b0:enable,1'b1:disable.Bit[0] free list 0,Bit[1] free
                                             * list 1,Bit[2] free list 2,...Bit[31] free list 31.
                                             */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_DIS_DE_ALLOC_U;

/* **
* Union name :    SM_ABUF_FLRC_ST
* @brief               This is the Sm abuf0 free list reclaim status register.This is used by the software to scan the
reclaimed working state.

* Description:
*/
typedef union tagUnSmAbufFlrcSt {
    struct tagStSmAbufFlrcSt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 28; /* * [31:4]This register is for reboundary function.  It will be accessed by the software
                           during the re-boundary operation.bit[31:4] rclm_cnt:reclaim counter,this counter
                           compare with rclm_num, rclm_cnt=rclm_num means relcaim will be finished. */
        unsigned int reserved : 1;      /* * [3:3]reserved */
        unsigned int wlistCleaning : 1; /* * [2:2]wlist clean status register.1'b0:wlist is not being clean.1'b1:wlist
                                         * is being clean.
                                         */
        unsigned int rlistCleaning : 1; /* * [1:1]reclaim list clean status register.1'b0:  The reclaim list is not
                                         * being clean.1'b1:  The reclaim list is being clean.
                                         */
        unsigned int doneRclm : 1;      /* * [0:0]free list reclaim states.1'b0: Reclaim not done;1'b1: Reclaim done. */
#else
        unsigned int doneRclm : 1;      /* * [0:0]free list reclaim states.1'b0: Reclaim not done;1'b1: Reclaim done. */
        unsigned int rlistCleaning : 1; /* * [1:1]reclaim list clean status register.1'b0:  The reclaim list is not
                                         * being clean.1'b1:  The reclaim list is being clean.
                                         */
        unsigned int wlistCleaning : 1; /* * [2:2]wlist clean status register.1'b0:wlist is not being clean.1'b1:wlist
                                         * is being clean.
                                         */
        unsigned int reserved : 1;      /* * [3:3]reserved */
        unsigned int ctp : 28; /* * [31:4]This register is for reboundary function.  It will be accessed by the software
                           during the re-boundary operation.bit[31:4] rclm_cnt:reclaim counter,this counter
                           compare with rclm_num, rclm_cnt=rclm_num means relcaim will be finished. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FLRC_ST_U;

/* **
* Union name :    SM_ABUF_EMPTY_FL
* @brief               This is the Sm abuf0 free list empty status register.This is used by software to scan whether
regarding list is empty or not.

* Description:
*/
typedef union tagUnSmAbufEmptyFl {
    struct tagStSmAbufEmptyFl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 32; /* * [31:0]Free list empty bitmap,index with free list id:  1'b0: Not empty;1'b1: both
                                * pre-fetch lifo and external DDR is Empty.
                                */
#else
        unsigned int ctp : 32; /* * [31:0]Free list empty bitmap,index with free list id:  1'b0: Not empty;1'b1: both
                                * pre-fetch lifo and external DDR is Empty.
                                */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_EMPTY_FL_U;

/* **
* Union name :    SM_ABUF_FULL_FL
* @brief               This is the Sm abuf0 free list full/almost full status register.This is used by the software to
scan whether the list is full, almost full, or none of the above
                       .
* Description:
*/
typedef union tagUnSmAbufFullFl {
    struct tagStSmAbufFullFl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 32; /* * [31:0]Free list full status bitmap.  Index with free list id:  1'b0: Not full;1'b1:
                           Full.Full means the total free nodes number in both pre-fetch lifo and external DD
                           R is equal or larger than the Total number configured in list info. */
#else
        unsigned int ctp : 32; /* * [31:0]Free list full status bitmap.  Index with free list id:  1'b0: Not full;1'b1:
                           Full.Full means the total free nodes number in both pre-fetch lifo and external DD
                           R is equal or larger than the Total number configured in list info. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_FULL_FL_U;

/* **
* Union name :    SM_ABUF_ST_WM_GROW
* @brief               This is the Sm abuf0 free list grow watermark status register.This is used by the softeware to
scan whether the free list is in status that need to grow.

* Description:
*/
typedef union tagUnSmAbufStWmGrow {
    struct tagStSmAbufStWmGrow {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for growth. Index with free list ID.  1'b0: Used
                           watermark is lower than the growth threshold;1'b1: Used watermark is more than the growth
                           threshold.NOTE:this state update when rtl or csr write list info,so if want to change new
                           watermark and total cnt,must change watermark first.
                            */
#else
        unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for growth. Index with free list ID.  1'b0: Used
                           watermark is lower than the growth threshold;1'b1: Used watermark is more than the growth
                           threshold.NOTE:this state update when rtl or csr write list info,so if want to change new
                           watermark and total cnt,must change watermark first.
                            */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_ST_WM_GROW_U;

/* **
* Union name :    SM_ABUF_ST_WM_SHRINK
* @brief               This is the Sm abuf0 free list shrink watermark status register.This is used by the softeware to
scan whether the free list is in a shrink status.

* Description:
*/
typedef union tagUnSmAbufStWmShrink {
    struct tagStSmAbufStWmShrink {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for shrink. Index with free list ID.  1'b0:
                           Watermark is lower than the shrink threshold;1'b1: Watermark is more than the shrink thr
                           eshold.NOTE:this state update when rtl or csr write list info,so if want to change new
                           watermark and total cnt,must change watermark first.
                            */
#else
        unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for shrink. Index with free list ID.  1'b0:
                           Watermark is lower than the shrink threshold;1'b1: Watermark is more than the shrink thr
                           eshold.NOTE:this state update when rtl or csr write list info,so if want to change new
                           watermark and total cnt,must change watermark first.
                            */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_ST_WM_SHRINK_U;

/* **
* Union name :    SM_ABUF_CNT_SEL0
* @brief               This is the Sm abuf0 csr counter select config register.This is used to select which free list
must be counted.

* Description:
*/
typedef union tagUnSmAbufCntSel0 {
    struct tagStSmAbufCntSel0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int cnt3EventSel : 3; /* * [31:29]counter 3 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt3SrcSel : 5;   /* * [28:24]counter 3 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt2EventSel : 3; /* * [23:21]counter 2 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt2SrcSel : 5;   /* * [20:16]counter 2 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt1EventSel : 3; /* * [15:13]counter 1 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt1SrcSel : 5;   /* * [12:8]counter 1 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt0EventSel : 3; /* * [7:5]counter 0 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt0SrcSel : 5;   /* * [4:0]counter 5 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
#else
        unsigned int cnt0SrcSel : 5;   /* * [4:0]counter 5 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt0EventSel : 3; /* * [7:5]counter 0 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt1SrcSel : 5;   /* * [12:8]counter 1 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt1EventSel : 3; /* * [15:13]counter 1 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt2SrcSel : 5;   /* * [20:16]counter 2 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt2EventSel : 3; /* * [23:21]counter 2 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt3SrcSel : 5;   /* * [28:24]counter 3 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt3EventSel : 3; /* * [31:29]counter 3 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_CNT_SEL0_U;

/* **
* Union name :    SM_ABUF_CNT_SEL1
* @brief               Sm abuf ireq list status register.Sw can use this register to judge if the request queue is empty
or not.

* Description:
*/
typedef union tagUnSmAbufCntSel1 {
    struct tagStSmAbufCntSel1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 10; /* * [31:22]reserved */
        unsigned int cntEnable : 6; /* * [21:16]counter enable/disable register.User can config this member to enable or
                                 diable any counter.Cnt_en[0] counter 0 enable/disabale cfg bit.Cnt_en[1] counter 0 enab
                                 le/disabale cfg bit.Cnt_en[2] counter 0 enable/disabale cfg bit.Cnt_en[3] counter 0
                                 enable/disabale cfg bit.Cnt_en[4] counter 0 enable/disabale cfg bit.Cnt_en[5
                                 ] counter 0 enable/disabale cfg bit. */
        unsigned int cnt5EventSel : 3; /* * [15:13]counter 5 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt5SrcSel : 5;   /* * [12:8]counter 5 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt4EventSel : 3; /* * [7:5]counter 4 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt4SrcSel : 5;   /* * [4:0]counter 4 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
#else
        unsigned int cnt4SrcSel : 5;   /* * [4:0]counter 4 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt4EventSel : 3; /* * [7:5]counter 4 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cnt5SrcSel : 5;   /* * [12:8]counter 5 source selection.5'h0:count free list0,5'h1:count free
                                        * list1,....5'h31:count free list 31.
                                        */
        unsigned int cnt5EventSel : 3; /* * [15:13]counter 5 event selection.3'b000:count get op.3'b001:count put
                                        * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld
                                        * op.3'b101:count st op.
                                        */
        unsigned int cntEnable : 6; /* * [21:16]counter enable/disable register.User can config this member to enable or
                                 diable any counter.Cnt_en[0] counter 0 enable/disabale cfg bit.Cnt_en[1] counter 0 enab
                                 le/disabale cfg bit.Cnt_en[2] counter 0 enable/disabale cfg bit.Cnt_en[3] counter 0
                                 enable/disabale cfg bit.Cnt_en[4] counter 0 enable/disabale cfg bit.Cnt_en[5
                                 ] counter 0 enable/disabale cfg bit. */
        unsigned int reserved : 10; /* * [31:22]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_CNT_SEL1_U;

/* **
* Union name :    SM_ABUF_COUNTER0
* @brief               This is the Sm abuf0 allocate free node count register.This is used to count the free nodes that
have been allocated successfully by abuf0.

* Description:
*/
typedef union tagUnSmAbufCounter0 {
    struct tagStSmAbufCounter0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufCounter0 : 32; /* * [31:0]Counter 0 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#else
        unsigned int smAbufCounter0 : 32; /* * [31:0]Counter 0 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_COUNTER0_U;

/* **
* Union name :    SM_ABUF_COUNTER1
* @brief               This is the Sm abuf0 de-allocate free node count register.This is used to count the free nodes
that have been de-allocated successfully by abuf0.

* Description:
*/
typedef union tagUnSmAbufCounter1 {
    struct tagStSmAbufCounter1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufCounter1 : 32; /* * [31:0]Counter 1 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#else
        unsigned int smAbufCounter1 : 32; /* * [31:0]Counter 1 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_COUNTER1_U;

/* **
* Union name :    SM_ABUF_COUNTER2
* @brief               This is the allocate failed operation count register.This is used to count the total number of
failed allocate operation attempts.

* Description:
*/
typedef union tagUnSmAbufCounter2 {
    struct tagStSmAbufCounter2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufCounter2 : 32; /* * [31:0]Counter 2 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#else
        unsigned int smAbufCounter2 : 32; /* * [31:0]Counter 2 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_COUNTER2_U;

/* **
* Union name :    SM_ABUF_COUNTER3
* @brief               This is the Sm abuf0 de-allocate failed operation count register.This is used to count the total
number of failed de-allocate operation attempts.

* Description:
*/
typedef union tagUnSmAbufCounter3 {
    struct tagStSmAbufCounter3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufCounter3 : 32; /* * [31:0]Counter 3 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#else
        unsigned int smAbufCounter3 : 32; /* * [31:0]Counter 3 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_COUNTER3_U;

/* **
* Union name :    SM_ABUF_COUNTER4
* @brief               This is the Sm abuf0 total pre-fetch load operation count register.This is used to count the
total number of pre-fetched load operations.

* Description:
*/
typedef union tagUnSmAbufCounter4 {
    struct tagStSmAbufCounter4 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufCounter4 : 32; /* * [31:0]Counter 4 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#else
        unsigned int smAbufCounter4 : 32; /* * [31:0]Counter 4 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_COUNTER4_U;

/* **
* Union name :    SM_ABUF_COUNTER5
* @brief               This is the Sm abuf0 total pre-fetch store operation count register.This is used to count the
total pre-fetched  store operations.

* Description:
*/
typedef union tagUnSmAbufCounter5 {
    struct tagStSmAbufCounter5 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smAbufCounter5 : 32; /* * [31:0]Counter 5 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#else
        unsigned int smAbufCounter5 : 32; /* * [31:0]Counter 5 used to count one event which configured in
                                             SM_ABUF_CNT_SEL. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_COUNTER5_U;

/* **
* Union name :    SM_ABUF_PFETCH_FLAG
* @brief               Sm abuf pre-fetch load/store setup flag.This is used to record which free list has initiated
pre-fetch load/store operation.

* Description:
*/
typedef union tagUnSmAbufPfetchFlag {
    struct tagStSmAbufPfetchFlag {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 32; /* * [31:0]record the pfe-fetch load/store status of 32 free lists.Bit[0]:list 0
                           pre-fetch ld/st flag.Bit[1]:list 0 pre-fetch ld/st flag....Bit[31]:list 0 pre-fetch ld/st
                           flag.Corresponding bit will be set when one list has initiated pre-fetch load or store
                           operation to smmc.Corresponding bit will be clear when one list has recei ve pre-fetch load
                           reture or store grant from smmc. */
#else
        unsigned int ctp : 32; /* * [31:0]record the pfe-fetch load/store status of 32 free lists.Bit[0]:list 0
                           pre-fetch ld/st flag.Bit[1]:list 0 pre-fetch ld/st flag....Bit[31]:list 0 pre-fetch ld/st
                           flag.Corresponding bit will be set when one list has initiated pre-fetch load or store
                           operation to smmc.Corresponding bit will be clear when one list has recei ve pre-fetch load
                           reture or store grant from smmc. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_PFETCH_FLAG_U;

/* **
* Union name :    SM_ABUF_IREQ_LIST_STA
* @brief               Sm abuf ireq list status register.Sw can use this register to judge if the request queue is empty
or not.

* Description:
*/
typedef union tagUnSmAbufIreqListSta {
    struct tagStSmAbufIreqListSta {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 32; /* * [31:0]ctp[0]:request queue status of free list0,ctp[1]:request queue status of free
                           list1,...ctp[31]:request queue status of free list31.1'b0:request queue is empty,1
                           'b1:request queue is not empty. */
#else
        unsigned int ctp : 32; /* * [31:0]ctp[0]:request queue status of free list0,ctp[1]:request queue status of free
                           list1,...ctp[31]:request queue status of free list31.1'b0:request queue is empty,1
                           'b1:request queue is not empty. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_IREQ_LIST_STA_U;

/* **
* Union name :    SM_ABUF_TAIL_MISS0
* @brief               This is the SM abuf0 tail miss capture register.  This is used to capture the information of the
tail-missed free list.

* Description:
*/
typedef union tagUnSmAbufTailMiss0 {
    struct tagStSmAbufTailMiss0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:  Trigger is disable1:  Trigger enableAbuf0 compares tail
                                      pointer in external DDR with tail pointer in internal list_info,if they are
                                      mismatched,this bit will be set,and regarding information will be captured in
                                      capture_data. */
        unsigned long long captureData : 63;  /* * [62:0]Capture regarding information of the free list whose tail has
                                    missed. capture low 64bit of the following information;bit[29:0] list old
                                    tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list
                                    counterbit[122:118] list id. */
#else
        unsigned long long captureData : 63;  /* * [62:0]Capture regarding information of the free list whose tail has
                                    missed. capture low 64bit of the following information;bit[29:0] list old
                                    tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list
                                    counterbit[122:118] list id. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:  Trigger is disable1:  Trigger enableAbuf0 compares tail
                                      pointer in external DDR with tail pointer in internal list_info,if they are
                                      mismatched,this bit will be set,and regarding information will be captured in
                                      capture_data. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SM_ABUF_TAIL_MISS0_U;

/* **
* Union name :    SM_ABUF_TAIL_MISS1
* @brief               This is the SM abuf0 tail miss capture register.  This is used to capture the information of the
tail-missed free list.

* Description:
*/
typedef union tagUnSmAbufTailMiss1 {
    struct tagStSmAbufTailMiss1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long triggerEnable : 1; /* * [63:63]0:  Trigger is disable1:  Trigger enableAbuf0 compares tail
                                      pointer in external DDR with tail pointer in internal list_info,if they are
                                      mismatched,this bit will be set,and regarding information will be captured in
                                      capture_data. */
        unsigned long long captureData : 63;  /* * [62:0]Capture regarding information of the free list whose tail has
                                    missed.capture high 64bit of the following information;bit[29:0] list old
                                    tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list
                                    counterbit[122:118] list id. */
#else
        unsigned long long captureData : 63;  /* * [62:0]Capture regarding information of the free list whose tail has
                                    missed.capture high 64bit of the following information;bit[29:0] list old
                                    tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list
                                    counterbit[122:118] list id. */
        unsigned long long triggerEnable : 1; /* * [63:63]0:  Trigger is disable1:  Trigger enableAbuf0 compares tail
                                      pointer in external DDR with tail pointer in internal list_info,if they are
                                      mismatched,this bit will be set,and regarding information will be captured in
                                      capture_data. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SM_ABUF_TAIL_MISS1_U;

/* **
* Union name :    SM_ABUF_CNT_LIFO_PFETCH_0
* @brief               This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number
in each pfetch lifo.

* Description:
*/
typedef union tagUnSmAbufCntLifoPfetch0 {
    struct tagStSmAbufCntLifoPfetch0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to
                           free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre
                           -fetch lifo has a 4-bit free node counter.  Bit[3:0] pre-fetch lifo counter of free list
                           0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of
                           free list 31, */
#else
        unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to
                           free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre
                           -fetch lifo has a 4-bit free node counter.  Bit[3:0] pre-fetch lifo counter of free list
                           0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of
                           free list 31, */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SM_ABUF_CNT_LIFO_PFETCH_0_U;

/* **
* Union name :    SM_ABUF_CNT_LIFO_PFETCH_1
* @brief               This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number
in each pfetch lifo.

* Description:
*/
typedef union tagUnSmAbufCntLifoPfetch1 {
    struct tagStSmAbufCntLifoPfetch1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to
                           free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre
                           -fetch lifo has a 4-bit free node counter.  Bit[3:0] pre-fetch lifo counter of free list
                           0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of
                           free list 31, */
#else
        unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to
                           free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre
                           -fetch lifo has a 4-bit free node counter.  Bit[3:0] pre-fetch lifo counter of free list
                           0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of
                           free list 31, */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SM_ABUF_CNT_LIFO_PFETCH_1_U;

/* **
* Union name :    SM_ABUF_CNT_LIFO_PFETCH_2
* @brief               This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number
in each pfetch lifo.

* Description:
*/
typedef union tagUnSmAbufCntLifoPfetch2 {
    struct tagStSmAbufCntLifoPfetch2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 28; /* * [31:4]reserved. */
        unsigned int ctp : 4; /* * [3:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to free list
                           0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre -fetch lifo
                           has a 4-bit free node counter.  Bit[3:0] pre-fetch lifo counter of Rebounding free list.
                            */
#else
        unsigned int ctp : 4; /* * [3:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to free list
                           0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre -fetch lifo
                           has a 4-bit free node counter.  Bit[3:0] pre-fetch lifo counter of Rebounding free list.
                            */
        unsigned int reserved : 28;          /* * [31:4]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_CNT_LIFO_PFETCH_2_U;

/* **
 * Union name :    SM_ABUF_ECC_CFG
 * @brief               SMEG0_ABUF ECC function configration register
 * Description:
 */
typedef union tagUnSmAbufEccCfg {
    struct tagStSmAbufEccCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 24; /* * [31:8]Reserved */
        unsigned int reserved1 : 1;  /* * [7:7]Reserved */
        unsigned int lifoEccEn : 1; /* * [6:6]Bypass ECC function of lifo info memory1: enable ecc function0: bypass ecc
                                     * function
                                     */
        unsigned int lifo2bEccInjEn : 1; /* * [5:5]Enable to inject Dual ECC Error when read lifo memory0: disable1:
                                            enable */
        unsigned int lifo1bEccInjEn : 1; /* * [4:4]Enable to inject Single ECC Error when read lifo memory0: disable1:
                                            enable */
        unsigned int reserved2 : 1;      /* * [3:3]Reserved */
        unsigned int listInfoEccEn : 1; /* * [2:2]Enable ECC function of list info memory1: enable ecc function0: bypass
                                         * ecc function
                                         */
        unsigned int listInfo2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read list info memory0:
                                                disable1: enable */
        unsigned int listInfo1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read list info memory0:
                                                disable1: enable */
#else
        unsigned int listInfo1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read list info memory0:
                                                disable1: enable */
        unsigned int listInfo2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read list info memory0:
                                                disable1: enable */
        unsigned int listInfoEccEn : 1; /* * [2:2]Enable ECC function of list info memory1: enable ecc function0: bypass
                                         * ecc function
                                         */
        unsigned int reserved2 : 1;     /* * [3:3]Reserved */
        unsigned int lifo1bEccInjEn : 1; /* * [4:4]Enable to inject Single ECC Error when read lifo memory0: disable1:
                                            enable */
        unsigned int lifo2bEccInjEn : 1; /* * [5:5]Enable to inject Dual ECC Error when read lifo memory0: disable1:
                                            enable */
        unsigned int lifoEccEn : 1; /* * [6:6]Bypass ECC function of lifo info memory1: enable ecc function0: bypass ecc
                                     * function
                                     */
        unsigned int reserved1 : 1; /* * [7:7]Reserved */
        unsigned int reserved0 : 24;    /* * [31:8]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_ECC_CFG_U;

/* **
 * Union name :    SM_ABUF_ECC_1B_ERR_INT
 * @brief               1 bit error sticky register
 * Description:
 */
typedef union tagUnSmAbufEcc1bErrInt {
    struct tagStSmAbufEcc1bErrInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;       /* * [31:2]Sticky[0]:list info 1 bit ECC error;Sticky[1]:pfetch lifo 1 bit ECC
                                     error;Sticky[6:2]: which address of list info has 1 bit error.Sticky[13:7]  which address
                                     of pfetch lifo has 1bit error.Sticky[29:14]: reserved */
        unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */
        unsigned int errorBit : 1;      /* * [0:0]0: No error found.  1: Error found. */
#else
        unsigned int errorBit : 1;      /* * [0:0]0: No error found.  1: Error found. */
        unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */
        unsigned int sticky : 30;       /* * [31:2]Sticky[0]:list info 1 bit ECC error;Sticky[1]:pfetch lifo 1 bit ECC
                                     error;Sticky[6:2]: which address of list info has 1 bit error.Sticky[13:7]  which address
                                     of pfetch lifo has 1bit error.Sticky[29:14]: reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_ECC_1B_ERR_INT_U;

/* **
 * Union name :    SM_ABUF_ECC_2B_ERR_INT
 * @brief               2 bit error sticky register
 * Description:
 */
typedef union tagUnSmAbufEcc2bErrInt {
    struct tagStSmAbufEcc2bErrInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;       /* * [31:2]Sticky[0]:list info 2 bit ECC error;Sticky[1]:pfetch lifo 2 bit ECC
                                     error;Sticky[6:2]: which address of list info has 2 bit error.Sticky[13:7]  which address
                                     of pfetch lifo has 2 bit error.Sticky[29:14]: reserved */
        unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */
        unsigned int errorBit : 1;      /* * [0:0]0: No error found.  1: Error found. */
#else
        unsigned int errorBit : 1;      /* * [0:0]0: No error found.  1: Error found. */
        unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */
        unsigned int sticky : 30;       /* * [31:2]Sticky[0]:list info 2 bit ECC error;Sticky[1]:pfetch lifo 2 bit ECC
                                     error;Sticky[6:2]: which address of list info has 2 bit error.Sticky[13:7]  which address
                                     of pfetch lifo has 2 bit error.Sticky[29:14]: reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SM_ABUF_ECC_2B_ERR_INT_U;


/* **
 * Union name :    SMEG0_AGET_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmeg0AgetVersion {
    struct tagStSmeg0AgetVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0AgetVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smeg0AgetVersion : 32; /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_VERSION_U;

/* **
 * Union name :    SMEG0_AGET_CFG
 * @brief               age table configure registers
 * Description:
 */
typedef union tagUnSmeg0AgetCfg {
    struct tagStSmeg0AgetCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 11;   /* * [31:21]reserved */
        unsigned int smeg0Cnt1Cfg : 2; /* * [20:19]smeg0_cnt1 configure:bit0:enable,    1-enable, 0-disable;bit1:source
                                        * select,    1-counter for smeg0_ALU    0-counter for smeg0_AGET
                                        */
        unsigned int smeg0Cnt0Cfg : 2; /* * [18:17]smeg0_cnt0 configure:as same as the Comments of smeg0_cnt1_cfg */
        unsigned int smegCoreMemInitStart : 1; /* * [16:16]A posedge of this bit will triggle memory in smeg_core init
                                                  start. */
        unsigned int memRet1n : 1;             /* * [15:15]control of memory pin RET1N */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int reserved1 : 7; /* * [7:1]reserved */
        unsigned int memChkEn : 1;  /* * [0:0]memory parity check enable.1'b0:disable all memories err check.1'b1:enable
                                     * all memories err check.
                                     */
#else
        unsigned int memChkEn : 1;  /* * [0:0]memory parity check enable.1'b0:disable all memories err check.1'b1:enable
                                     * all memories err check.
                                     */
        unsigned int reserved1 : 7; /* * [7:1]reserved */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int memRet1n : 1;  /* * [15:15]control of memory pin RET1N */
        unsigned int smegCoreMemInitStart : 1; /* * [16:16]A posedge of this bit will triggle memory in smeg_core init
                                                  start. */
        unsigned int smeg0Cnt0Cfg : 2; /* * [18:17]smeg0_cnt0 configure:as same as the Comments of smeg0_cnt1_cfg */
        unsigned int smeg0Cnt1Cfg : 2; /* * [20:19]smeg0_cnt1 configure:bit0:enable,    1-enable, 0-disable;bit1:source
                                        * select,    1-counter for smeg0_ALU    0-counter for smeg0_AGET
                                        */
        unsigned int reserved0 : 11;   /* * [31:21]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_CFG_U;

/* **
 * Union name :    SMEG0_AGET_INT_VECTOR
 * @brief               interrupt vector
 * Description:
 */
typedef union tagUnSmeg0AgetIntVector {
    struct tagStSmeg0AgetIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                     * register0:interrupt disable1:interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;       /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                        * register0:interrupt disable1:interrupt enable
                                        */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_INT_VECTOR_U;

/* **
 * Union name :    SMEG0_AGET_INT
 * @brief               interrupt data
 * Description:
 */
typedef union tagUnSmeg0AgetInt {
    struct tagStSmeg0AgetInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 14;     /* * [15:2] */
        unsigned int intData : 2;       /* * [1:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 2;   /* * [1:0]interrupt masked field,it is the collection of the error bits from the
                                     * corresponding error registers on the sheet
                                     */
        unsigned int reserved : 14; /* * [15:2] */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_INT_U;

/* **
 * Union name :    SMEG0_AGET_INT_MASK
 * @brief               interrupt mask
 * Description:
 */
typedef union tagUnSmeg0AgetIntMask {
    struct tagStSmeg0AgetIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 14;     /* * [15:2] */
        unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 14;     /* * [15:2] */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_INT_MASK_U;

/* **
 * Union name :    SMEG0_AGET_MEM_PRTY_ERR
 * @brief               SMEG0_AGET age flag memory parity error
 * Description:
 */
typedef union tagUnSmeg0AgetMemPrtyErr {
    struct tagStSmeg0AgetMemPrtyErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is off.
                                    * [29:8]: reserved[7:0] memory index of parity error
                                    */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is off.
                                         * [29:8]: reserved[7:0] memory index of parity error
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_MEM_PRTY_ERR_U;

/* **
 * Union name :    SMEG0_AGET_BOUNDARY_ERR
 * @brief               SMEG0_AGET operation is out of the table boundary
 * Description:
 */
typedef union tagUnSmeg0AgetBoundaryErr {
    struct tagStSmeg0AgetBoundaryErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is off.
                               others: reserved[13:8]:instance ID[7:0]: operation index of error (the original index rece
                               ived from SMEG1) */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is off.
                                    others: reserved[13:8]:instance ID[7:0]: operation index of error (the original index rece
                                    ived from SMEG1) */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_BOUNDARY_ERR_U;

/* **
 * Union name :    SMEG0_AGET_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmeg0AgetIndrectCtrl {
    struct tagStSmeg0AgetIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0AgetIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect
                                          access invalid, including operation done and timeout (initial value or logic
                                          clear);1’b1: indirect ac cess valid (software set). */
        unsigned int smeg0AgetIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read.
                                              */
        unsigned int smeg0AgetIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                              * done;2’b01: indirect access timeout;Others: reserved.
                                              */
        unsigned int smeg0AgetIndirTab : 4;  /* * [27:24]It specifies memory group or table. 4’b0000: base address
                                              * table;4’b0001: age flag memory;others:reserved
                                              */
        unsigned int smeg0AgetIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory
                                          address in one group or internal address of the table.Base address table:
                                          bit7:2: instance ID; bit7 is RSV in SMF Age flag MEM:  bit9:2: memory
                                          indexbit[1:0] word select:   0:reserved,   1:mem_dat[95:64]   2:mem_dat[63:32]
                                          3:mem_dat[31:0]Note: for accessing
                                          base address table,bit[1:0] should be 2'h3. */
#else
        unsigned int smeg0AgetIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory
                                          address in one group or internal address of the table.Base address table:
                                          bit7:2: instance ID; bit7 is RSV in SMF Age flag MEM:  bit9:2: memory
                                          indexbit[1:0] word select:   0:reserved,   1:mem_dat[95:64]   2:mem_dat[63:32]
                                          3:mem_dat[31:0]Note: for accessing
                                          base address table,bit[1:0] should be 2'h3. */
        unsigned int smeg0AgetIndirTab : 4;   /* * [27:24]It specifies memory group or table. 4’b0000: base address
                                               * table;4’b0001: age flag memory;others:reserved
                                               */
        unsigned int smeg0AgetIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                              * done;2’b01: indirect access timeout;Others: reserved.
                                              */
        unsigned int smeg0AgetIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read.
                                              */
        unsigned int smeg0AgetIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect
                                          access invalid, including operation done and timeout (initial value or logic
                                          clear);1’b1: indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_INDRECT_CTRL_U;

/* **
 * Union name :    SMEG0_AGET_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmeg0AgetIndrectTimeout {
    struct tagStSmeg0AgetIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0AgetIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smeg0AgetIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMEG0_AGET_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmeg0AgetIndrectData {
    struct tagStSmeg0AgetIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0AgetIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write:
                                           Software write data to these registes and then enable indirect access, logic
                                           will send these data to target.When operation read:  Logic write data to
                                           these registers and refresh xxx_indir_stat, software will get these data from
                                           target.
                                           */
#else
        unsigned int smeg0AgetIndirData : 32;    /* * [31:0]It specifies the indirect access data:When operation write:
                                              Software write data to these registes and then enable indirect access, logic
                                              will send these data to target.When operation read:  Logic write data to
                                              these registers and refresh xxx_indir_stat, software will get these data from
                                              target.
                                              */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_AGET_INDRECT_DATA_U;

/* **
 * Union name :    SMEG_CORE_MEM_INIT
 * @brief               smeg core memory init done flag
 * Description:
 */
typedef union tagUnSmegCoreMemInit {
    struct tagStSmegCoreMemInit {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 31; /* * [31:1]reserved. */
        unsigned int done : 1;      /* * [0:0]1'b1: indicate memory init done;1'b0: memory init not done */
#else
        unsigned int done : 1;                   /* * [0:0]1'b1: indicate memory init done;1'b0: memory init not done */
        unsigned int reserved : 31;              /* * [31:1]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG_CORE_MEM_INIT_U;

/* **
 * Union name :    SMEG0_CNT0
 * @brief               SMEG0 Counter 0
 * Description:
 */
typedef union tagUnSmeg0Cnt0 {
    struct tagStSmeg0Cnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0Cnt0 : 32; /* * [31:0]SMEG0 received request numbers;Used to Counter the numbers of received
                                      * request numbers of smeg0 age table or smeg0 ALU module
                                      */
#else
        unsigned int smeg0Cnt0 : 32; /* * [31:0]SMEG0 received request numbers;Used to Counter the numbers of received
                                      * request numbers of smeg0 age table or smeg0 ALU module
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_CNT0_U;

/* **
 * Union name :    SMEG0_CNT1
 * @brief               SMEG0 Counter 1
 * Description:
 */
typedef union tagUnSmeg0Cnt1 {
    struct tagStSmeg0Cnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0Cnt1 : 32; /* * [31:0]SMEG0 returned grant numbers;Used to Counter the numbers of grant
                                      * numbers of smeg0 age table or smeg0 ALU module
                                      */
#else
        unsigned int smeg0Cnt1 : 32; /* * [31:0]SMEG0 returned grant numbers;Used to Counter the numbers of grant
                                      * numbers of smeg0 age table or smeg0 ALU module
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_CNT1_U;


/* **
 * Union name :    SMEG0_LU_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmeg0LuVersion {
    struct tagStSmeg0LuVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smeg0LuVersion : 32;   /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_VERSION_U;

/* **
 * Union name :    SMEG0_LU_CHK_ENABLE_CFG
 * @brief               configuration register for memory check enbale
 * Description:
 */
typedef union tagUnSmeg0LuChkEnableCfg {
    struct tagStSmeg0LuChkEnableCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 8; /* * [31:24]reserved */
        unsigned int memRet1n : 1;  /* * [23:23]control of memory pin RET1N */
        unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                     * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                     * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                     */
        unsigned int reserved1 : 4; /* * [7:4]reserved */
        unsigned int pipe0MemChkEnable : 1; /* * [3:3]0:disable1:enable */
        unsigned int pipe1MemChkEnable : 1; /* * [2:2]0:disable1:enable */
        unsigned int flitFifoChkEnable : 1; /* * [1:1]0:disable1:enable */
        unsigned int reserved2 : 1;         /* * [0:0]reserved */
#else
        unsigned int reserved2 : 1;         /* * [0:0]reserved */
        unsigned int flitFifoChkEnable : 1; /* * [1:1]0:disable1:enable */
        unsigned int pipe1MemChkEnable : 1; /* * [2:2]0:disable1:enable */
        unsigned int pipe0MemChkEnable : 1; /* * [3:3]0:disable1:enable */
        unsigned int reserved1 : 4;         /* * [7:4]reserved */
        unsigned int tpRamTmod : 8;         /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                             * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                             */
        unsigned int spRamTmod : 7;    /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                        * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                        */
        unsigned int memRet1n : 1;     /* * [23:23]control of memory pin RET1N */
        unsigned int reserved0 : 8;    /* * [31:24]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_CHK_ENABLE_CFG_U;

/* **
 * Union name :    SMEG0_LU_INT_VECTOR
 * @brief               interrupt vector
 * Description:
 */
typedef union tagUnSmeg0LuIntVector {
    struct tagStSmeg0LuIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                     * register0:interrupt disable1:interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;       /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                        * register0:interrupt disable1:interrupt enable
                                        */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_INT_VECTOR_U;

/* **
 * Union name :    SMEG0_LU_INT
 * @brief               interrupt data
 * Description:
 */
typedef union tagUnSmeg0LuInt {
    struct tagStSmeg0LuInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 9;      /* * [15:7] */
        unsigned int intData : 7;       /* * [6:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 7;   /* * [6:0]interrupt masked field,it is the collection of the error bits from the
                                     * corresponding error registers on the sheet
                                     */
        unsigned int reserved : 9;  /* * [15:7] */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_INT_U;

/* **
 * Union name :    SMEG0_LU_INT_MASK
 * @brief               interrupt mask
 * Description:
 */
typedef union tagUnSmeg0LuIntMask {
    struct tagStSmeg0LuIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 9;      /* * [15:7] */
        unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 9;      /* * [15:7] */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_INT_MASK_U;

/* **
 * Union name :    SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR
 * @brief               SMEG0_LOOKUP_PIPE0MEM ECC 1bit error
 * Description:
 */
typedef union tagUnSmeg0LuPipe0MemEccCrtErr {
    struct tagStSmeg0LuPipe0MemEccCrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is off.
                                    * [29:7]: reserved[6:0] pipe0_mem index of ecc error
                                    */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is off.
                                         * [29:7]: reserved[6:0] pipe0_mem index of ecc error
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_U;

/* **
 * Union name :    SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR
 * @brief               SMEG0_LOOKUP_PIPE0MEM ECC multi-bit error
 * Description:
 */
typedef union tagUnSmeg0LuPipe0MemEccUncrtErr {
    struct tagStSmeg0LuPipe0MemEccUncrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is off.
                                    * [29:7]: reserved[6:0] pipe0_mem index of ecc error
                                    */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is off.
                                         * [29:7]: reserved[6:0] pipe0_mem index of ecc error
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_U;

/* **
 * Union name :    SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR
 * @brief               SMEG0_LOOKUP_PIPE1MEM ECC 1bit error
 * Description:
 */
typedef union tagUnSmeg0LuPipe1MemEccCrtErr {
    struct tagStSmeg0LuPipe1MemEccCrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is off.
                                    * [29:9]: reserved[8:0] pipe0_mem index of ecc error
                                    */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is off.
                                         * [29:9]: reserved[8:0] pipe0_mem index of ecc error
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_U;

/* **
 * Union name :    SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR
 * @brief               SMEG0_LOOKUP_PIPE1MEM ECC multi-bit error
 * Description:
 */
typedef union tagUnSmeg0LuPipe1MemEccUncrtErr {
    struct tagStSmeg0LuPipe1MemEccUncrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is off.
                                    * [29:9]: reserved[8:0] pipe0_mem index of ecc error
                                    */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is off.
                                         * [29:9]: reserved[8:0] pipe0_mem index of ecc error
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_U;

/* **
 * Union name :    SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR
 * @brief               SMEG0_LU_FLITFIFO 1bit error
 * Description:
 */
typedef union tagUnSmeg0LuFlitfifoMemEccCrtErr {
    struct tagStSmeg0LuFlitfifoMemEccCrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is
                               off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error
                               flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]:
                               ctrl_fifo mem check error flagIn flit,each 32bit generates a even parity error bit,i f
                               anyone happen parity error,will be triggered a flit error flag.15 bit ctrl_info generate a
                               even parity error flag. Any error flag will be triggered this inter rupt. */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is
                                    off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error
                                    flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]:
                                    ctrl_fifo mem check error flagIn flit,each 32bit generates a even parity error bit,i f
                                    anyone happen parity error,will be triggered a flit error flag.15 bit ctrl_info generate a
                                    even parity error flag. Any error flag will be triggered this inter rupt. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_U;

/* **
 * Union name :    SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR
 * @brief               SMEG0_LU_FLITFIFO multi-bit error
 * Description:
 */
typedef union tagUnSmeg0LuFlitfifoMemEccUncrtErr {
    struct tagStSmeg0LuFlitfifoMemEccUncrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is
                               off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error
                               flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]:
                               reservedIn flit,each 32bit generates a even parity error bit,if anyone happen parity
                               error,will be triggered a flit error flag.15 bit ctrl_info generate a even parity error
                               flag. Any error flag will be triggered this interrupt.
                                */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is
                                    off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error
                                    flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]:
                                    reservedIn flit,each 32bit generates a even parity error bit,if anyone happen parity
                                    error,will be triggered a flit error flag.15 bit ctrl_info generate a even parity error
                                    flag. Any error flag will be triggered this interrupt.
                                     */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_U;

/* **
 * Union name :    SMEG0_LU_SW_ERR
 * @brief               BTREE engine detected software fatal error
 * Description:
 */
typedef union tagUnSmeg0LuSwErr {
    struct tagStSmeg0LuSwErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;  /* * [31:2]captures error state of the first error, capture even if mask is off.
                               [31:8]:engine result 29:6 bits.[7]: API length error;[6]: SW err[5:2]: SW error cause(Plea
                               se refer to SEMG0_lookup uArch spec) */
        unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int err : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int err : 1;           /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErr : 1;      /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is off.
                                    [31:8]:engine result 29:6 bits.[7]: API length error;[6]: SW err[5:2]: SW error cause(Plea
                                    se refer to SEMG0_lookup uArch spec) */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_SW_ERR_U;

/* **
 * Union name :    SMEG0_LU_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmeg0LuIndrectCtrl {
    struct tagStSmeg0LuIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                       invalid, including operation done and timeout (initial value or logic
                                       clear);1’b1: indirect ac cess valid (software set). */
        unsigned int smeg0LuIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read.
                                            */
        unsigned int smeg0LuIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                            * done;2’b01: indirect access timeout;Others: reserved.
                                            */
        unsigned int smeg0LuIndirTab : 4;  /* * [27:24]It specifies memory group or table.    0x0:pipe0 memory 0x1:pipe1
                                            * memory   others:reserved
                                            */
        unsigned int smeg0LuIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory
                                        address in one group or internal address of the table.index [12:4]: pipe1_mem
                                        index for 390 entriesin dex [10:4]: pipe0_mem index for 118 entriesindex [3:0]:
                                        offset of one entry0x0-0x6: reserved, no mapping0x7: data[287:256]0x8:
                                        data[255:224]0x9: data[223:192]0x a: data[191:160]0xb: data[159:128]0xc:
                                        data[127:96]0xd: data[95:64]0xe: data[63:32]0xf: data[31:0]
                                         */
#else
        unsigned int smeg0LuIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory
                                        address in one group or internal address of the table.index [12:4]: pipe1_mem
                                        index for 390 entriesin dex [10:4]: pipe0_mem index for 118 entriesindex [3:0]:
                                        offset of one entry0x0-0x6: reserved, no mapping0x7: data[287:256]0x8:
                                        data[255:224]0x9: data[223:192]0x a: data[191:160]0xb: data[159:128]0xc:
                                        data[127:96]0xd: data[95:64]0xe: data[63:32]0xf: data[31:0]
                                         */
        unsigned int smeg0LuIndirTab : 4;  /* * [27:24]It specifies memory group or table.    0x0:pipe0 memory 0x1:pipe1
                                            * memory   others:reserved
                                            */
        unsigned int smeg0LuIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                            * done;2’b01: indirect access timeout;Others: reserved.
                                            */
        unsigned int smeg0LuIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read.
                                            */
        unsigned int smeg0LuIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                       invalid, including operation done and timeout (initial value or logic
                                       clear);1’b1: indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_INDRECT_CTRL_U;

/* **
 * Union name :    SMEG0_LU_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmeg0LuIndrectTimeout {
    struct tagStSmeg0LuIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smeg0LuIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMEG0_LU_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmeg0LuIndrectData {
    struct tagStSmeg0LuIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write:
                                         Software write data to these registes and then enable indirect access, logic
                                         will send these data to target.When operation read:  Logic write data to these
                                         registers and refresh xxx_indir_stat, software will get these data from target.
                                         */
#else
        unsigned int smeg0LuIndirData : 32;    /* * [31:0]It specifies the indirect access data:When operation write:
                                            Software write data to these registes and then enable indirect access, logic
                                            will send these data to target.When operation read:  Logic write data to these
                                            registers and refresh xxx_indir_stat, software will get these data from target.
                                            */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_INDRECT_DATA_U;

/* **
* Union name :    SMEG0_LU_ERR_INJ_CFG
* @brief               configuration register for error injection of FIFO memories. FIFO doesn't support CSR access.
Software can set error inject enable bit to test error handling.

* Description:
*/
typedef union tagUnSmeg0LuErrInjCfg {
    struct tagStSmeg0LuErrInjCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 26;           /* * [31:6]reserved */
        unsigned int flitfUncrtErrInjReq : 1; /* * [5:5]ECC uncrt err injection requestion;err injection start when
                                           posedge of this bit is detected; After Err injection start, err is injected
                                           when a memory read is is sued to the memory. Enable memory check, when use
                                           this err inection function. */
        unsigned int flitfCrtErrInjReq : 1; /* * [4:4]ECC crt err injection requestion;err injection start when posedge
                                         of this bit is detected; After Err injection start, err is injected when a
                                         memory read is issu ed to the memory.Enable memory check, when use this err
                                         inection function. */
        unsigned int pipe1UncrtErrInjReq : 1; /* * [3:3]ECC uncrt err injection requestion;err injection start when
                                           posedge of this bit is detected; After Err injection start, err is injected
                                           when a memory read is is sued to the memory. Enable memory check, when use
                                           this err inection function. */
        unsigned int pipe1CrtErrInjReq : 1; /* * [2:2]ECC crt err injection requestion;err injection start when posedge
                                         of this bit is detected; After Err injection start, err is injected when a
                                         memory read is issu ed to the memory.Enable memory check, when use this err
                                         inection function. */
        unsigned int pipe0UncrtErrInjReq : 1; /* * [1:1]ECC uncrt err injection requestion;err injection start when
                                           posedge of this bit is detected; After Err injection start, err is injected
                                           when a memory read is is sued to the memory. Enable memory check, when use
                                           this err inection function. */
        unsigned int pipe0CrtErrInjReq : 1; /* * [0:0]ECC crt err injection requestion;err injection start when posedge
                                         of this bit is detected; After Err injection start, err is injected when a
                                         memory read is issu ed to the memory.Enable memory check, when use this err
                                         inection function. */
#else
        unsigned int pipe0CrtErrInjReq : 1; /* * [0:0]ECC crt err injection requestion;err injection start when posedge
                                         of this bit is detected; After Err injection start, err is injected when a
                                         memory read is issu ed to the memory.Enable memory check, when use this err
                                         inection function. */
        unsigned int pipe0UncrtErrInjReq : 1; /* * [1:1]ECC uncrt err injection requestion;err injection start when
                                           posedge of this bit is detected; After Err injection start, err is injected
                                           when a memory read is is sued to the memory. Enable memory check, when use
                                           this err inection function. */
        unsigned int pipe1CrtErrInjReq : 1; /* * [2:2]ECC crt err injection requestion;err injection start when posedge
                                         of this bit is detected; After Err injection start, err is injected when a
                                         memory read is issu ed to the memory.Enable memory check, when use this err
                                         inection function. */
        unsigned int pipe1UncrtErrInjReq : 1; /* * [3:3]ECC uncrt err injection requestion;err injection start when
                                           posedge of this bit is detected; After Err injection start, err is injected
                                           when a memory read is is sued to the memory. Enable memory check, when use
                                           this err inection function. */
        unsigned int flitfCrtErrInjReq : 1; /* * [4:4]ECC crt err injection requestion;err injection start when posedge
                                         of this bit is detected; After Err injection start, err is injected when a
                                         memory read is issu ed to the memory.Enable memory check, when use this err
                                         inection function. */
        unsigned int flitfUncrtErrInjReq : 1; /* * [5:5]ECC uncrt err injection requestion;err injection start when
                                           posedge of this bit is detected; After Err injection start, err is injected
                                           when a memory read is is sued to the memory. Enable memory check, when use
                                           this err inection function. */
        unsigned int reserved : 26;           /* * [31:6]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_ERR_INJ_CFG_U;

/* **
 * Union name :    SMEG0_LU_CNT_CFG
 * @brief               counter related configuration register
 * Description:
 */
typedef union tagUnSmeg0LuCntCfg {
    struct tagStSmeg0LuCntCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 21;    /* * [31:11]reserved */
        unsigned int engEventGrp : 3;  /* * [10:8]engine enent group select;3'h0 : sel group 0 event to count;3'h1 : sel
                                    group 1 event to count;3'h2 : sel group 2 event to count;3'h3 : sel group 3 event to
                                    coun t;3'h4 : sel all group event to count;others: reserved */
        unsigned int cnt3EventSel : 1; /* * [7:7]0: engine_event[3];1: outgoing_msg */
        unsigned int cnt2EventSel : 1; /* * [6:6]0: engine_event[2]; 1: outgoing_flit */
        unsigned int cnt1EventSel : 1; /* * [5:5]0: engine_event[1];1: incoming msg */
        unsigned int cnt0EventSel : 1; /* * [4:4]0: engine_event[0];1: incoming flit. */
        unsigned int cntEnable : 4; /* * [3:0]each bit is mapping to one counter.setting 1 means enable, seeting 0 means
                                 disable4'bxxx1: SMEG0_LU_CNT0_ENABLE4'bxx1x: SMEG0_LU_CNT1_ENABLE4'bx1xx: SMEG0_LU_CN
                                 T2_ENABLE4'b1xxx: SMEG0_LU_CNT3_ENABLE */
#else
        unsigned int cntEnable : 4; /* * [3:0]each bit is mapping to one counter.setting 1 means enable, seeting 0 means
                                 disable4'bxxx1: SMEG0_LU_CNT0_ENABLE4'bxx1x: SMEG0_LU_CNT1_ENABLE4'bx1xx: SMEG0_LU_CN
                                 T2_ENABLE4'b1xxx: SMEG0_LU_CNT3_ENABLE */
        unsigned int cnt0EventSel : 1; /* * [4:4]0: engine_event[0];1: incoming flit. */
        unsigned int cnt1EventSel : 1; /* * [5:5]0: engine_event[1];1: incoming msg */
        unsigned int cnt2EventSel : 1; /* * [6:6]0: engine_event[2]; 1: outgoing_flit */
        unsigned int cnt3EventSel : 1; /* * [7:7]0: engine_event[3];1: outgoing_msg */
        unsigned int engEventGrp : 3;  /* * [10:8]engine enent group select;3'h0 : sel group 0 event to count;3'h1 : sel
                                    group 1 event to count;3'h2 : sel group 2 event to count;3'h3 : sel group 3 event to
                                    coun t;3'h4 : sel all group event to count;others: reserved */
        unsigned int reserved : 21;    /* * [31:11]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_CNT_CFG_U;

/* **
 * Union name :    SMEG0_LU_CNT0
 * @brief               counter0
 * Description:
 */
typedef union tagUnSmeg0LuCnt0 {
    struct tagStSmeg0LuCnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuCnt0 : 32; /* * [31:0] */
#else
        unsigned int smeg0LuCnt0 : 32; /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_CNT0_U;

/* **
 * Union name :    SMEG0_LU_CNT1
 * @brief               counter1
 * Description:
 */
typedef union tagUnSmeg0LuCnt1 {
    struct tagStSmeg0LuCnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuCnt1 : 32; /* * [31:0] */
#else
        unsigned int smeg0LuCnt1 : 32; /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_CNT1_U;

/* **
 * Union name :    SMEG0_LU_CNT2
 * @brief               counter2
 * Description:
 */
typedef union tagUnSmeg0LuCnt2 {
    struct tagStSmeg0LuCnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuCnt2 : 32; /* * [31:0] */
#else
        unsigned int smeg0LuCnt2 : 32; /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_CNT2_U;

/* **
 * Union name :    SMEG0_LU_CNT3
 * @brief               counter3
 * Description:
 */
typedef union tagUnSmeg0LuCnt3 {
    struct tagStSmeg0LuCnt3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg0LuCnt3 : 32; /* * [31:0] */
#else
        unsigned int smeg0LuCnt3 : 32; /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_CNT3_U;

/* **
 * Union name :    SMEG0_LU_CTP
 * @brief               SMEG0 Profile Register for performance monitor.
 * Description:
 */
typedef union tagUnSmeg0LuCtp {
    struct tagStSmeg0LuCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 22;         /* * [31:10]reserved */
        unsigned int numInOriginalFifo : 5; /* * [9:5]number of APIs in original_fifo. */
        unsigned int numInResultFifo : 5;   /* * [4:0]number of commands in result_fifo. Those commands are completed in
                                             * smeg0, and waits for forwarding to smeg1
                                             */
#else
        unsigned int numInResultFifo : 5;   /* * [4:0]number of commands in result_fifo. Those commands are completed in
                                             * smeg0, and waits for forwarding to smeg1
                                             */
        unsigned int numInOriginalFifo : 5; /* * [9:5]number of APIs in original_fifo. */
        unsigned int reserved : 22;         /* * [31:10]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG0_LU_CTP_U;


/* **
 * Union name :    SMEG1_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmeg1Version {
    struct tagStSmeg1Version {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1Version : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smeg1Version : 32;     /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_VERSION_U;

/* **
* Union name :    SMEG1_CFG0
* @brief               Smart Memory Infra Engine Group1 (SMEG1) configuration register . This is used to configure
additional features,  and for debug.

* Description:
*/
typedef union tagUnSmeg1Cfg0 {
    struct tagStSmeg1Cfg0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int rpHaltThreadMaxNum : 6; /* * [31:26]maximus halted threads number, 0 - halt 1 thread at most;1 -
                                          halt 2 thread at most;……;N - halt N+1 thread at most;Notes: Make sure N < 16
                                          in SML and N < 32 in S MF; */
        unsigned int btInstId : 6; /* * [25:20]Btree instance ID, all btree API use the same instance ID to access
                                memory, including Btree node/LT/AGE table; The base address of these table should be
                                configu re use this instance ID, not instance ID from API */
        unsigned int rpInlldLlIvldEn : 1; /* * [19:19]Configure for MISC_F engine RDMA inline load API. last cache line
                                       cache invalid enable control:1'b1 - send cache invalid command for the last cache
                                       line access by the current API;1'b0 - only when all the data of the last cache
                                       line is load to cpi, send cache invalid command for the cache line, else dont
                                       send cache inva lid command for the last cache line */
        unsigned int memChkEn : 1; /* * [18:18]memory check enable.1'b0:disable all memories err check.1'b1:enable all
                                    * memories err check.
                                    */
        unsigned int msbThreadCfg : 1;     /* * [17:17]0:msb thread is used as special thread only used in response
                                        channel;1:msb thread is used as normal thread only used in request channel;*NOTE:
                                        This bit and smir .smir_cfg.msb_thread_cfg should be configure the same value */
        unsigned int tcdThdId : 6;         /* * [16:11]which thread's tcd map to tcd ctp */
        unsigned int haltOnRunawayErr : 1; /* * [10:10]halt thread on runaway error    1:  halt the thread in smeg1 0:
                                              no halt */
        unsigned int ctpActiveBits : 1; /* * [9:9]1:  runaway ctp transmits thread active bits 0: runaway ctp transmits
                                         * runaway threads
                                         */
        unsigned int haltSwErr1 : 1;    /* * [8:8]halt thread on software error1.      1:  halt the thread in smeg1 when
                                     engine detected sw_err1;Send message for the thread and SR if LL is issued ever. 0: no
                                     h alt, no SEND/SR operation; */
        unsigned int haltOnEbit : 1;    /* * [7:7]halt thread on ebit with load return, store return,get put return or
                                         * wakeup.    1:  halt the thread in smeg1      0:  no halt
                                         */
        unsigned int haltSwErr : 1;   /* * [6:6]halt thread on software error.      1:  halt the thread in smeg1      0:
                                       * no halt
                                       */
        unsigned int prememCount : 4; /* * [5:2]This is the number of allowed preload or prestore operations before
                                       * issuing a thread from the install issue queue
                                       */
        unsigned int preloadFairness : 1;     /* * [1:1]1:  turn on  preload fairness0:  do not use preload fairness */
        unsigned int detectRunawayThread : 1; /* * [0:0]1:  detect runaway thread    0:  do not detect any runaway
                                               * thread.Attention:before turn on this bit, should configure
                                               * smeg1_runaway_cfg first.
                                               */
#else
        unsigned int detectRunawayThread : 1; /* * [0:0]1:  detect runaway thread    0:  do not detect any runaway
                                               * thread.Attention:before turn on this bit, should configure
                                               * smeg1_runaway_cfg first.
                                               */
        unsigned int preloadFairness : 1;     /* * [1:1]1:  turn on  preload fairness0:  do not use preload fairness */
        unsigned int prememCount : 4; /* * [5:2]This is the number of allowed preload or prestore operations before
                                       * issuing a thread from the install issue queue
                                       */
        unsigned int haltSwErr : 1;   /* * [6:6]halt thread on software error.      1:  halt the thread in smeg1      0:
                                       * no halt
                                       */
        unsigned int haltOnEbit : 1;  /* * [7:7]halt thread on ebit with load return, store return,get put return or
                                       * wakeup.    1:  halt the thread in smeg1      0:  no halt
                                       */
        unsigned int haltSwErr1 : 1;  /* * [8:8]halt thread on software error1.      1:  halt the thread in smeg1 when
                                   engine detected sw_err1;Send message for the thread and SR if LL is issued ever. 0: no
                                   h alt, no SEND/SR operation; */
        unsigned int ctpActiveBits : 1; /* * [9:9]1:  runaway ctp transmits thread active bits 0: runaway ctp transmits
                                         * runaway threads
                                         */
        unsigned int haltOnRunawayErr : 1; /* * [10:10]halt thread on runaway error    1:  halt the thread in smeg1 0:
                                              no halt */
        unsigned int tcdThdId : 6;         /* * [16:11]which thread's tcd map to tcd ctp */
        unsigned int msbThreadCfg : 1;     /* * [17:17]0:msb thread is used as special thread only used in response
                                        channel;1:msb thread is used as normal thread only used in request channel;*NOTE:
                                        This bit and smir .smir_cfg.msb_thread_cfg should be configure the same value */
        unsigned int memChkEn : 1; /* * [18:18]memory check enable.1'b0:disable all memories err check.1'b1:enable all
                                    * memories err check.
                                    */
        unsigned int rpInlldLlIvldEn : 1; /* * [19:19]Configure for MISC_F engine RDMA inline load API. last cache line
                                       cache invalid enable control:1'b1 - send cache invalid command for the last cache
                                       line access by the current API;1'b0 - only when all the data of the last cache
                                       line is load to cpi, send cache invalid command for the cache line, else dont
                                       send cache inva lid command for the last cache line */
        unsigned int btInstId : 6; /* * [25:20]Btree instance ID, all btree API use the same instance ID to access
                                memory, including Btree node/LT/AGE table; The base address of these table should be
                                configu re use this instance ID, not instance ID from API */
        unsigned int rpHaltThreadMaxNum : 6; /* * [31:26]maximus halted threads number, 0 - halt 1 thread at most;1 -
                                          halt 2 thread at most;……;N - halt N+1 thread at most;Notes: Make sure N < 16
                                          in SML and N < 32 in S MF; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_CFG0_U;

/* **
 * Union name :    SMEG1_CFG1
 * @brief               Smart Memory Infra Engine Group1 (SMEG1) configuration register .
 * Description:
 */
typedef union tagUnSmeg1Cfg1 {
    struct tagStSmeg1Cfg1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 12; /* * [31:20]Software can use this register to do memory power and timing configure;
                                     */
        unsigned int fidrUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when
                                          posedge of this bit is detected; After Err injection start, err is injected
                                          when a memory read is is sued to the memory. Enable memory check, when use
                                          this err inection function. */
        unsigned int fidrCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge
                                        of this bit is detected; After Err injection start, err is injected when a
                                        memory read is issu ed to the memory.Enable memory check, when use this err
                                        inection function. */
        unsigned int rpUncrtErrInjReq : 1; /* * [17:17]as same as fidr_uncrt_err_inj_req; only for the ECC protected
                                            * memory in SMEG1 excepted FIDR
                                            */
        unsigned int rpCrtErrInjReq : 1; /* * [16:16]as same as fidr_crt_err_inj_req; only for the ECC protected memory
                                          * in SMEG1 excepted FIDR
                                          */
        unsigned int memRet1n : 1;       /* * [15:15]control of memory pin RET1N */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                     * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                     */
#else
        unsigned int tpRamTmod : 8;          /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                              * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                              */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int memRet1n : 1;  /* * [15:15]control of memory pin RET1N */
        unsigned int rpCrtErrInjReq : 1; /* * [16:16]as same as fidr_crt_err_inj_req; only for the ECC protected memory
                                          * in SMEG1 excepted FIDR
                                          */
        unsigned int rpUncrtErrInjReq : 1; /* * [17:17]as same as fidr_uncrt_err_inj_req; only for the ECC protected
                                            * memory in SMEG1 excepted FIDR
                                            */
        unsigned int fidrCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge
                                        of this bit is detected; After Err injection start, err is injected when a
                                        memory read is issu ed to the memory.Enable memory check, when use this err
                                        inection function. */
        unsigned int fidrUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when
                                          posedge of this bit is detected; After Err injection start, err is injected
                                          when a memory read is is sued to the memory. Enable memory check, when use
                                          this err inection function. */
        unsigned int reserved : 12; /* * [31:20]Software can use this register to do memory power and timing configure;
                                     */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_CFG1_U;

/* **
* Union name :    SMEG1_RUNAWAY_CFG
* @brief               Smart Memory Infra Engine Group1 (SMEG1) Runaway sampling count configuration register.   In the
normal operation, this can be used as a watch dog timer for 16 or 64 threads in a smart memory tile.
* Description:
*/
typedef union tagUnSmeg1RunawayCfg {
    struct tagStSmeg1RunawayCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1RunawayCfg : 32; /* * [31:0]The value programmed in this register is used to measure the life
                                       span of an active thread. The maximum value of this watch dog timer is 4s. Once a
                                       thread is ca ught as a runaway, the kill pending bit in the scoreboard is
                                       asserted and the thread is prohibited from reissuing until software clears the
                                       bit.*NOTE: 1. If you want to change the default runaway time, please close the
                                       runaway detect function, update the ruaway time, then re-open the runaway
                                       detected operation.2. the D efault value is 200ms @1GHz clock */
#else
        unsigned int smeg1RunawayCfg : 32; /* * [31:0]The value programmed in this register is used to measure the life
                                       span of an active thread. The maximum value of this watch dog timer is 4s. Once a
                                       thread is ca ught as a runaway, the kill pending bit in the scoreboard is
                                       asserted and the thread is prohibited from reissuing until software clears the
                                       bit.*NOTE: 1. If you want to change the default runaway time, please close the
                                       runaway detect function, update the ruaway time, then re-open the runaway
                                       detected operation.2. the D efault value is 200ms @1GHz clock */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_RUNAWAY_CFG_U;

/* **
 * Union name :    SMEG1_THREAD_ENABLE_CFG
 * @brief               Thread enable configure; bitmap for 16/32 thread in smeg1
 * Description:
 */
typedef union tagUnSmeg1ThreadEnableCfg {
    struct tagStSmeg1ThreadEnableCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1ThreadEnableCfg : 32; /* * [31:0]thread disable configure; bitmap for 16/32 thread in smeg1;
                                            bit0 is for thread0, bit1 is for thread 1, and so on; (bit31:16 is reserved
                                            in SML)1'b1: thread is e nable1'b0: thread is disable, this thread will be
                                            not allocated;*NOTE: if msb_thread_cfg is configured to allocate the MSB
                                            thread to response channel, then the MSB (bit15 in SML/bit31 in SMF) of this
                                            field should be enable*NOTE: not configure all 0's to this field.(when MSB
                                            is allocated to response channel, not configu
                                            re all 0's to the other valid fields) */
#else
        unsigned int smeg1ThreadEnableCfg : 32; /* * [31:0]thread disable configure; bitmap for 16/32 thread in smeg1;
                                            bit0 is for thread0, bit1 is for thread 1, and so on; (bit31:16 is reserved
                                            in SML)1'b1: thread is e nable1'b0: thread is disable, this thread will be
                                            not allocated;*NOTE: if msb_thread_cfg is configured to allocate the MSB
                                            thread to response channel, then the MSB (bit15 in SML/bit31 in SMF) of this
                                            field should be enable*NOTE: not configure all 0's to this field.(when MSB
                                            is allocated to response channel, not configu
                                            re all 0's to the other valid fields) */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_THREAD_ENABLE_CFG_U;

/* **
 * Union name :    SMEG1_TM_TS_FAST2
 * @brief               timer wheel control info
 * Description:
 */
typedef union tagUnSmeg1TmTsFast2 {
    struct tagStSmeg1TmTsFast2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTsFast2 : 32; /* * [31:0]This register Includes fast timer wheel 0~3, {Timer wheel 0, Timer
                                      wheel 1,Timer wheel 2, Timer wheel 3}One timer wheel's info:bit[7] :Valid,
                                      Indicate this timi ng wheel is validbit[6:5] Spoke Mode,        00: 256 spokes 01:
                                      512 spokes       10: 1024 spokes       11: 2048 spokes bit[4:0] Spoke Tick Scale,
                                      Indicate s how many ticks this timing wheel’s spoke takes, one tick time is equal
                                      to based unit tick time, 1us.one spoke tick =  2^spoke tick scale
                                       */
#else
        unsigned int smeg1TmTsFast2 : 32; /* * [31:0]This register Includes fast timer wheel 0~3, {Timer wheel 0, Timer
                                      wheel 1,Timer wheel 2, Timer wheel 3}One timer wheel's info:bit[7] :Valid,
                                      Indicate this timi ng wheel is validbit[6:5] Spoke Mode,        00: 256 spokes 01:
                                      512 spokes       10: 1024 spokes       11: 2048 spokes bit[4:0] Spoke Tick Scale,
                                      Indicate s how many ticks this timing wheel’s spoke takes, one tick time is equal
                                      to based unit tick time, 1us.one spoke tick =  2^spoke tick scale
                                       */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TS_FAST2_U;

/* **
 * Union name :    SMEG1_TM_TS_FAST3
 * @brief               TIMER engine wheel control info
 * Description:
 */
typedef union tagUnSmeg1TmTsFast3 {
    struct tagStSmeg1TmTsFast3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTsFast3 : 32; /* * [31:0]This register Includes slow timer wheel 4~5, {Timer wheel 4, Timer
                                           * wheel 5,Reserved 16 bit}timer wheel info data structure is same with fast
                                           * timer wheel info.
                                           */
#else
        unsigned int smeg1TmTsFast3 : 32; /* * [31:0]This register Includes slow timer wheel 4~5, {Timer wheel 4, Timer
                                           * wheel 5,Reserved 16 bit}timer wheel info data structure is same with fast
                                           * timer wheel info.
                                           */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TS_FAST3_U;

/* **
 * Union name :    SMEG1_TM_TS_SLOW0
 * @brief               TIMER engine control info
 * Description:
 */
typedef union tagUnSmeg1TmTsSlow0 {
    struct tagStSmeg1TmTsSlow0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTsSlow0 : 32; /* * [31:0][31:2]: reserved[1]: indicate core clock's frequency0: 900MHz1:
                                       600MHz[0]: CAR engine use type of timestamp. If chip support DFS, select global
                                       timestamp.0: use local timestamp1: use global timestamp */
#else
        unsigned int smeg1TmTsSlow0 : 32; /* * [31:0][31:2]: reserved[1]: indicate core clock's frequency0: 900MHz1:
                                       600MHz[0]: CAR engine use type of timestamp. If chip support DFS, select global
                                       timestamp.0: use local timestamp1: use global timestamp */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TS_SLOW0_U;

/* **
 * Union name :    SMEG1_TM_TS_SLOW1
 * @brief               TIMER engine control info
 * Description:
 */
typedef union tagUnSmeg1TmTsSlow1 {
    struct tagStSmeg1TmTsSlow1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTsSlow1 : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual
                                      entry size and cache line size.value indcates:00: actual size/cache line szie =
                                      1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11:
                                      actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 15Bit [29:28]: entry
                                      14Bit [27: 26]: entry 13Bit [25:24]: entry 12Bit [23:22]: entry 11Bit [21:20]:
                                      entry 10Bit [19:18]: entry 9Bit [17:16]: entry 8Bit [15:14]: entry 7Bit [13:12]:
                                      entry 6Bit [11:10]: entry 5Bit [9:8]  : entry 4Bit [7:6]  : entry 3Bit [5:4]  :
                                      entry 2Bit [3:2]  : entry 1Bit [1:0]  : entry 0
                                       */
#else
        unsigned int smeg1TmTsSlow1 : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual
                                      entry size and cache line size.value indcates:00: actual size/cache line szie =
                                      1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11:
                                      actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 15Bit [29:28]: entry
                                      14Bit [27: 26]: entry 13Bit [25:24]: entry 12Bit [23:22]: entry 11Bit [21:20]:
                                      entry 10Bit [19:18]: entry 9Bit [17:16]: entry 8Bit [15:14]: entry 7Bit [13:12]:
                                      entry 6Bit [11:10]: entry 5Bit [9:8]  : entry 4Bit [7:6]  : entry 3Bit [5:4]  :
                                      entry 2Bit [3:2]  : entry 1Bit [1:0]  : entry 0
                                       */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TS_SLOW1_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG7
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg7 {
    struct tagStSmeg1TmTmtCfg7 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt31 : 8; /* * [31:24]timer engine memory type config for APIs whose service type is
                                    31:bit[7]: valid flag,        1: valid;       0: invalid;bit[6:4] Vcache index:
                                    Virtual cache Ind ex for context in FIARbit[3:0] Tag_type,Memory Tag Type, which is
                                    used to access context, and definitions are referred in stateful SM FS.
                                     */
        unsigned int smeg1TmTmt30 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 30
                                        */
        unsigned int smeg1TmTmt29 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 29
                                        */
        unsigned int smeg1TmTmt28 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 28
                                        */
#else
        unsigned int smeg1TmTmt28 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 28
                                        */
        unsigned int smeg1TmTmt29 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 29
                                        */
        unsigned int smeg1TmTmt30 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 30
                                        */
        unsigned int smeg1TmTmt31 : 8; /* * [31:24]timer engine memory type config for APIs whose service type is
                                    31:bit[7]: valid flag,        1: valid;       0: invalid;bit[6:4] Vcache index:
                                    Virtual cache Ind ex for context in FIARbit[3:0] Tag_type,Memory Tag Type, which is
                                    used to access context, and definitions are referred in stateful SM FS.
                                     */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG7_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG6
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg6 {
    struct tagStSmeg1TmTmtCfg6 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt27 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 27
                                        */
        unsigned int smeg1TmTmt26 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 26
                                        */
        unsigned int smeg1TmTmt25 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 25
                                        */
        unsigned int smeg1TmTmt24 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 24
                                        */
#else
        unsigned int smeg1TmTmt24 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 24
                                        */
        unsigned int smeg1TmTmt25 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 25
                                        */
        unsigned int smeg1TmTmt26 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 26
                                        */
        unsigned int smeg1TmTmt27 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 27
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG6_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG5
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg5 {
    struct tagStSmeg1TmTmtCfg5 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt23 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 23
                                        */
        unsigned int smeg1TmTmt22 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 22
                                        */
        unsigned int smeg1TmTmt21 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 21
                                        */
        unsigned int smeg1TmTmt20 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 20
                                        */
#else
        unsigned int smeg1TmTmt20 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 20
                                        */
        unsigned int smeg1TmTmt21 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 21
                                        */
        unsigned int smeg1TmTmt22 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 22
                                        */
        unsigned int smeg1TmTmt23 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 23
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG5_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG4
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg4 {
    struct tagStSmeg1TmTmtCfg4 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt19 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 19
                                        */
        unsigned int smeg1TmTmt18 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 18
                                        */
        unsigned int smeg1TmTmt17 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 17
                                        */
        unsigned int smeg1TmTmt16 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 16
                                        */
#else
        unsigned int smeg1TmTmt16 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 16
                                        */
        unsigned int smeg1TmTmt17 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 17
                                        */
        unsigned int smeg1TmTmt18 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 18
                                        */
        unsigned int smeg1TmTmt19 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 19
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG4_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG3
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg3 {
    struct tagStSmeg1TmTmtCfg3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt15 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 15
                                        */
        unsigned int smeg1TmTmt14 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 14
                                        */
        unsigned int smeg1TmTmt13 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 13
                                        */
        unsigned int smeg1TmTmt12 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 12
                                        */
#else
        unsigned int smeg1TmTmt12 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 12
                                        */
        unsigned int smeg1TmTmt13 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 13
                                        */
        unsigned int smeg1TmTmt14 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 14
                                        */
        unsigned int smeg1TmTmt15 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 15
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG3_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG2
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg2 {
    struct tagStSmeg1TmTmtCfg2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt11 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 11
                                        */
        unsigned int smeg1TmTmt10 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 10
                                        */
        unsigned int smeg1TmTmt9 : 8;  /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 9
                                        */
        unsigned int smeg1TmTmt8 : 8;  /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 8
                                        */
#else
        unsigned int smeg1TmTmt8 : 8;  /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 8
                                        */
        unsigned int smeg1TmTmt9 : 8;  /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 9
                                        */
        unsigned int smeg1TmTmt10 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 10
                                        */
        unsigned int smeg1TmTmt11 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 11
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG2_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG1
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg1 {
    struct tagStSmeg1TmTmtCfg1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt7 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 7
                                       */
        unsigned int smeg1TmTmt6 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 6
                                       */
        unsigned int smeg1TmTmt5 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 5
                                       */
        unsigned int smeg1TmTmt4 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 4
                                       */
#else
        unsigned int smeg1TmTmt4 : 8;  /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 4
                                        */
        unsigned int smeg1TmTmt5 : 8;  /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 5
                                        */
        unsigned int smeg1TmTmt6 : 8;  /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 6
                                        */
        unsigned int smeg1TmTmt7 : 8;  /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 7
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG1_U;

/* **
 * Union name :    SMEG1_TM_TMT_CFG0
 * @brief               TIMER engine type cfg
 * Description:
 */
typedef union tagUnSmeg1TmTmtCfg0 {
    struct tagStSmeg1TmTmtCfg0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmTmt3 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 3
                                       */
        unsigned int smeg1TmTmt2 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 2
                                       */
        unsigned int smeg1TmTmt1 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 1
                                       */
        unsigned int smeg1TmTmt0 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                       * service type is 0
                                       */
#else
        unsigned int smeg1TmTmt0 : 8;  /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 0
                                        */
        unsigned int smeg1TmTmt1 : 8;  /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 1
                                        */
        unsigned int smeg1TmTmt2 : 8;  /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 2
                                        */
        unsigned int smeg1TmTmt3 : 8;  /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose
                                        * service type is 3
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TM_TMT_CFG0_U;

/* **
 * Union name :    SMEG1_INT_VECTOR
 * @brief
 * Description:
 */
typedef union tagUnSmeg1IntVector {
    struct tagStSmeg1IntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes
                                    * 0 to clear.
                                    */
        unsigned int enable : 1;   /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                    * register0:interrupt disable1:interrupt enable
                                    */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;       /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                        * register0:interrupt disable1:interrupt enable
                                        */
        unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes
                                    * 0 to clear.
                                    */
        unsigned int reserved0 : 3;     /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_INT_VECTOR_U;

/* **
 * Union name :    SMEG1_INT
 * @brief
 * Description:
 */
typedef union tagUnSmeg1Int {
    struct tagStSmeg1Int {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 13;     /* * [15:3] */
        unsigned int intData : 3;       /* * [2:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 3;       /* * [2:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
        unsigned int reserved : 13;     /* * [15:3] */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_INT_U;

/* **
 * Union name :    SMEG1_INT_MASK
 * @brief
 * Description:
 */
typedef union tagUnSmeg1IntMask {
    struct tagStSmeg1IntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 13;     /* * [15:3] */
        unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 13;     /* * [15:3] */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_INT_MASK_U;

/* **
* Union name :    SMEG1_ENGINE_SW_ERR
* @brief               This is Smart Memory Infra Engine Group1 (SMEG1) engine software error log register.

* Description:
*/
typedef union tagUnSmeg1EngineSwErr {
    struct tagStSmeg1EngineSwErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off It
                              logs thread id, opcode of the failed API and instance id.Bi t[31]:sw_err1 is
                              detectedBit[30]:sw_err0 is detectedBit[29:26]:sw error codeBit[25:20]:RSVBit[19:14]:thread
                              id.Bit[13:8]:opcode.Bit[7:2]:instance id.
                               */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int errorBit : 1;      /* * [0:0]0:no error found1:error found */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error found1:error found */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int sticky : 30;     /* * [31:2]captures error state of the first error, capture even if mask is off It
                                  logs thread id, opcode of the failed API and instance id.Bi t[31]:sw_err1 is
                                  detectedBit[30]:sw_err0 is detectedBit[29:26]:sw error codeBit[25:20]:RSVBit[19:14]:thread
                                  id.Bit[13:8]:opcode.Bit[7:2]:instance id.
                                   */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_ENGINE_SW_ERR_U;

/* **
 * Union name :    SMEG1_ERR0
 * @brief               error register 0
 * Description:
 */
typedef union tagUnSmeg1Err0 {
    struct tagStSmeg1Err0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 14;   /* * [31:18]reserved. */
        unsigned int runawayMerr : 1; /* * [17:17] */
        unsigned int runawayErr : 1;  /* * [16:16]runaway error */
        unsigned int eccCrtMerr7 : 1; /* * [15:15] */
        unsigned int eccCrtErr7 : 1;  /* * [14:14]ecc correctable error is detected on memory ARR */
        unsigned int eccCrtMerr6 : 1; /* * [13:13] */
        unsigned int eccCrtErr6 : 1;  /* * [12:12]ecc correctable error is detected on memory tdr */
        unsigned int eccCrtMerr5 : 1; /* * [11:11] */
        unsigned int eccCrtErr5 : 1;  /* * [10:10]ecc correctable error is detected on memory etr1 */
        unsigned int eccCrtMerr4 : 1; /* * [9:9] */
        unsigned int eccCrtErr4 : 1;  /* * [8:8]ecc correctable error is detected on memory etr0 */
        unsigned int eccCrtMerr3 : 1; /* * [7:7] */
        unsigned int eccCrtErr3 : 1;  /* * [6:6]ecc correctable error is detected on memory esr */
        unsigned int eccCrtMerr2 : 1; /* * [5:5] */
        unsigned int eccCrtErr2 : 1;  /* * [4:4]ecc correctable error is detected on memory fidr */
        unsigned int eccCrtMerr1 : 1; /* * [3:3] */
        unsigned int eccCrtErr1 : 1;  /* * [2:2]ecc correctable error is detected on memory gpr1 */
        unsigned int eccCrtMerr0 : 1; /* * [1:1] */
        unsigned int eccCrtErr0 : 1;  /* * [0:0]ecc correctable error is detected on memory gpr0 */
#else
        unsigned int eccCrtErr0 : 1;  /* * [0:0]ecc correctable error is detected on memory gpr0 */
        unsigned int eccCrtMerr0 : 1; /* * [1:1] */
        unsigned int eccCrtErr1 : 1;  /* * [2:2]ecc correctable error is detected on memory gpr1 */
        unsigned int eccCrtMerr1 : 1; /* * [3:3] */
        unsigned int eccCrtErr2 : 1;  /* * [4:4]ecc correctable error is detected on memory fidr */
        unsigned int eccCrtMerr2 : 1; /* * [5:5] */
        unsigned int eccCrtErr3 : 1;  /* * [6:6]ecc correctable error is detected on memory esr */
        unsigned int eccCrtMerr3 : 1; /* * [7:7] */
        unsigned int eccCrtErr4 : 1;  /* * [8:8]ecc correctable error is detected on memory etr0 */
        unsigned int eccCrtMerr4 : 1; /* * [9:9] */
        unsigned int eccCrtErr5 : 1;  /* * [10:10]ecc correctable error is detected on memory etr1 */
        unsigned int eccCrtMerr5 : 1; /* * [11:11] */
        unsigned int eccCrtErr6 : 1;  /* * [12:12]ecc correctable error is detected on memory tdr */
        unsigned int eccCrtMerr6 : 1; /* * [13:13] */
        unsigned int eccCrtErr7 : 1;  /* * [14:14]ecc correctable error is detected on memory ARR */
        unsigned int eccCrtMerr7 : 1; /* * [15:15] */
        unsigned int runawayErr : 1;  /* * [16:16]runaway error */
        unsigned int runawayMerr : 1; /* * [17:17] */
        unsigned int reserved : 14;   /* * [31:18]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_ERR0_U;

/* **
 * Union name :    SMEG1_ERR0_MASK
 * @brief               error register 1
 * Description:
 */
typedef union tagUnSmeg1Err0Mask {
    struct tagStSmeg1Err0Mask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 23;      /* * [31:9]reserved. */
        unsigned int runawayErrMask : 1; /* * [8:8]err mask of runaway error */
        unsigned int eccCrtErrMask7 : 1; /* * [7:7]err mask of ECC correctable error 7 */
        unsigned int eccCrtErrMask6 : 1; /* * [6:6]err mask of ECC correctable error 6 */
        unsigned int eccCrtErrMask5 : 1; /* * [5:5]err mask of ECC correctable error 5 */
        unsigned int eccCrtErrMask4 : 1; /* * [4:4]err mask of ECC correctable error 4 */
        unsigned int eccCrtErrMask3 : 1; /* * [3:3]err mask of ECC correctable error 3 */
        unsigned int eccCrtErrMask2 : 1; /* * [2:2]err mask of ECC correctable error 2 */
        unsigned int eccCrtErrMask1 : 1; /* * [1:1]err mask of ECC correctable error 1 */
        unsigned int eccCrtErrMask0 : 1; /* * [0:0]err mask of ECC correctable error 0 */
#else
        unsigned int eccCrtErrMask0 : 1;   /* * [0:0]err mask of ECC correctable error 0 */
        unsigned int eccCrtErrMask1 : 1;   /* * [1:1]err mask of ECC correctable error 1 */
        unsigned int eccCrtErrMask2 : 1;   /* * [2:2]err mask of ECC correctable error 2 */
        unsigned int eccCrtErrMask3 : 1;   /* * [3:3]err mask of ECC correctable error 3 */
        unsigned int eccCrtErrMask4 : 1;   /* * [4:4]err mask of ECC correctable error 4 */
        unsigned int eccCrtErrMask5 : 1;   /* * [5:5]err mask of ECC correctable error 5 */
        unsigned int eccCrtErrMask6 : 1;   /* * [6:6]err mask of ECC correctable error 6 */
        unsigned int eccCrtErrMask7 : 1;   /* * [7:7]err mask of ECC correctable error 7 */
        unsigned int runawayErrMask : 1;   /* * [8:8]err mask of runaway error */
        unsigned int reserved : 23;        /* * [31:9]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_ERR0_MASK_U;

/* **
 * Union name :    SMEG1_ERR1
 * @brief
 * Description:
 */
typedef union tagUnSmeg1Err1 {
    struct tagStSmeg1Err1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16;     /* * [31:16]reserved. */
        unsigned int eccUncrtMerr7 : 1; /* * [15:15] */
        unsigned int eccUncrtErr7 : 1;  /* * [14:14]ECC uncorrectable error is detected on memory ARR */
        unsigned int eccUncrtMerr6 : 1; /* * [13:13] */
        unsigned int eccUncrtErr6 : 1;  /* * [12:12]ECC uncorrectable error is detected on memory tdr */
        unsigned int eccUncrtMerr5 : 1; /* * [11:11] */
        unsigned int eccUncrtErr5 : 1;  /* * [10:10]ECC uncorrectable error is detected on memory etr1 */
        unsigned int eccUncrtMerr4 : 1; /* * [9:9] */
        unsigned int eccUncrtErr4 : 1;  /* * [8:8]ECC uncorrectable error is detected on memory etr0 */
        unsigned int eccUncrtMerr3 : 1; /* * [7:7] */
        unsigned int eccUncrtErr3 : 1;  /* * [6:6]ECC uncorrectable error is detected on memory esr */
        unsigned int eccUncrtMerr2 : 1; /* * [5:5] */
        unsigned int eccUncrtErr2 : 1;  /* * [4:4]ECC uncorrectable error is detected on memory fidr */
        unsigned int eccUncrtMerr1 : 1; /* * [3:3] */
        unsigned int eccUncrtErr1 : 1;  /* * [2:2]ECC uncorrectable error is detected on memory gpr1 */
        unsigned int eccUncrtMerr0 : 1; /* * [1:1] */
        unsigned int eccUncrtErr0 : 1;  /* * [0:0]ECC uncorrectable error is detected on memory gpr0 */
#else
        unsigned int eccUncrtErr0 : 1;     /* * [0:0]ECC uncorrectable error is detected on memory gpr0 */
        unsigned int eccUncrtMerr0 : 1;    /* * [1:1] */
        unsigned int eccUncrtErr1 : 1;     /* * [2:2]ECC uncorrectable error is detected on memory gpr1 */
        unsigned int eccUncrtMerr1 : 1;    /* * [3:3] */
        unsigned int eccUncrtErr2 : 1;     /* * [4:4]ECC uncorrectable error is detected on memory fidr */
        unsigned int eccUncrtMerr2 : 1;    /* * [5:5] */
        unsigned int eccUncrtErr3 : 1;     /* * [6:6]ECC uncorrectable error is detected on memory esr */
        unsigned int eccUncrtMerr3 : 1;    /* * [7:7] */
        unsigned int eccUncrtErr4 : 1;     /* * [8:8]ECC uncorrectable error is detected on memory etr0 */
        unsigned int eccUncrtMerr4 : 1;    /* * [9:9] */
        unsigned int eccUncrtErr5 : 1;     /* * [10:10]ECC uncorrectable error is detected on memory etr1 */
        unsigned int eccUncrtMerr5 : 1;    /* * [11:11] */
        unsigned int eccUncrtErr6 : 1;     /* * [12:12]ECC uncorrectable error is detected on memory tdr */
        unsigned int eccUncrtMerr6 : 1;    /* * [13:13] */
        unsigned int eccUncrtErr7 : 1;     /* * [14:14]ECC uncorrectable error is detected on memory ARR */
        unsigned int eccUncrtMerr7 : 1;    /* * [15:15] */
        unsigned int reserved : 16;        /* * [31:16]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_ERR1_U;

/* **
 * Union name :    SMEG1_ERR1_MASK
 * @brief
 * Description:
 */
typedef union tagUnSmeg1Err1Mask {
    struct tagStSmeg1Err1Mask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 24;        /* * [31:8]reserved. */
        unsigned int eccUncrtErrMask7 : 1; /* * [7:7]err mask of ECC uncorrectable error 7 */
        unsigned int eccUncrtErrMask6 : 1; /* * [6:6]err mask of ECC uncorrectable error 6 */
        unsigned int eccUncrtErrMask5 : 1; /* * [5:5]err mask of ECC uncorrectable error 5 */
        unsigned int eccUncrtErrMask4 : 1; /* * [4:4]err mask of ECC uncorrectable error 4 */
        unsigned int eccUncrtErrMask3 : 1; /* * [3:3]err mask of ECC uncorrectable error 3 */
        unsigned int eccUncrtErrMask2 : 1; /* * [2:2]err mask of ECC uncorrectable error 2 */
        unsigned int eccUncrtErrMask1 : 1; /* * [1:1]err mask of ECC uncorrectable error 1 */
        unsigned int eccUncrtErrMask0 : 1; /* * [0:0]err mask of ECC uncorrectable error 0 */
#else
        unsigned int eccUncrtErrMask0 : 1; /* * [0:0]err mask of ECC uncorrectable error 0 */
        unsigned int eccUncrtErrMask1 : 1; /* * [1:1]err mask of ECC uncorrectable error 1 */
        unsigned int eccUncrtErrMask2 : 1; /* * [2:2]err mask of ECC uncorrectable error 2 */
        unsigned int eccUncrtErrMask3 : 1; /* * [3:3]err mask of ECC uncorrectable error 3 */
        unsigned int eccUncrtErrMask4 : 1; /* * [4:4]err mask of ECC uncorrectable error 4 */
        unsigned int eccUncrtErrMask5 : 1; /* * [5:5]err mask of ECC uncorrectable error 5 */
        unsigned int eccUncrtErrMask6 : 1; /* * [6:6]err mask of ECC uncorrectable error 6 */
        unsigned int eccUncrtErrMask7 : 1; /* * [7:7]err mask of ECC uncorrectable error 7 */
        unsigned int reserved : 24;        /* * [31:8]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_ERR1_MASK_U;

/* **
 * Union name :    SMEG1_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmeg1IndrectCtrl {
    struct tagStSmeg1IndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1IndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
        unsigned int smeg1IndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smeg1IndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smeg1IndirTab : 4;  /* * [27:24]It specifies memory group or table.    0x0:GPR0    0x1:GPR1 0x2:ESR
                                      0x3:FIDR   0x4:FICR   0x5:Scoreboard （read to get data for debug,and write to
                                      clear halt thread)   0x6:TDR (only in SMF)   0x7:ETR0(only in SMF)   0x8:ETR1(only
                                      in SMF)   0x9:ARR (only in SMF)   others:reservedNOTE：memory not support CSR write
                                      oper ation when the thread is running */
        unsigned int
            smeg1IndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one
                             group or internal address of the table.****** Comments for bit 9:3 - memory index ****
                             **For FICR:   8:3 instance ID, bit8 is RSV in SMFFor ScoreBoard:   7:3 thread ID, bit7 is
                             RSV in SMLFor fidr,   8:3 is instance id., bit8 is RSV in SMFFor gpr0/ gpr1,in SML:   9:8
                             reserved,   7:4 is thread id; in SMF,   9   reserved,   8:4 is thread id. Bit3 is logic
                             flit id.   For read gpr0,    if bit3 is 0, read Flit0 ;    if bit3 is 1, read flit2.   For
                             read gpr1,    if bit3 is 0, read flit1;    if bit3 is 1, read flit3.For ETR0/ETR1,   9
                             reserved,   8:4 is thread id. Bit3 is ETR id.   For read ETR0,    if bit3 is 0, read ID0 of
                             ETR0;    if bit3 is 1, read ID1 of ETR0.   For read ETR1,    if bit3 is 0, read ID0 of
                             ETR1;    if bit 3 is 1, read ID1 of ETR1.For esr, in SMF,   9 reserved,    if bit8 is
                             0,access normal esr0,    if bit8 is 1,access esr1. (RSV in 1822)   7:3 is thread id.in SML
                             ,   bit9:7 reserved,    6:3 is thread id. For TDR: (only in SMF)bit7:3 is thread ID******
                             Comments for bit 2:0 - word sel ******1. refer to FS AS for the detail data structure, and
                             ECC bit is read only2. DO NOT read write the word out of the MSB of the corresponding MEM
                             0x0:0x2
                              - reserved                                 0x3:  data[159:128] 0x4:  data[127:96] 0x5:
                             data[95:64]                                           0x6:  data[63:32] 0x7:  data[31:0]
                              */
#else
        unsigned int
            smeg1IndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one
                             group or internal address of the table.****** Comments for bit 9:3 - memory index ****
                             **For FICR:   8:3 instance ID, bit8 is RSV in SMFFor ScoreBoard:   7:3 thread ID, bit7 is
                             RSV in SMLFor fidr,   8:3 is instance id., bit8 is RSV in SMFFor gpr0/ gpr1,in SML:   9:8
                             reserved,   7:4 is thread id; in SMF,   9   reserved,   8:4 is thread id. Bit3 is logic
                             flit id.   For read gpr0,    if bit3 is 0, read Flit0 ;    if bit3 is 1, read flit2.   For
                             read gpr1,    if bit3 is 0, read flit1;    if bit3 is 1, read flit3.For ETR0/ETR1,   9
                             reserved,   8:4 is thread id. Bit3 is ETR id.   For read ETR0,    if bit3 is 0, read ID0 of
                             ETR0;    if bit3 is 1, read ID1 of ETR0.   For read ETR1,    if bit3 is 0, read ID0 of
                             ETR1;    if bit 3 is 1, read ID1 of ETR1.For esr, in SMF,   9 reserved,    if bit8 is
                             0,access normal esr0,    if bit8 is 1,access esr1. (RSV in 1822)   7:3 is thread id.in SML
                             ,   bit9:7 reserved,    6:3 is thread id. For TDR: (only in SMF)bit7:3 is thread ID******
                             Comments for bit 2:0 - word sel ******1. refer to FS AS for the detail data structure, and
                             ECC bit is read only2. DO NOT read write the word out of the MSB of the corresponding MEM
                             0x0:0x2
                              - reserved                                 0x3:  data[159:128] 0x4:  data[127:96] 0x5:
                             data[95:64]                                           0x6:  data[63:32] 0x7:  data[31:0]
                              */
        unsigned int smeg1IndirTab : 4;  /* * [27:24]It specifies memory group or table.    0x0:GPR0    0x1:GPR1 0x2:ESR
                                      0x3:FIDR   0x4:FICR   0x5:Scoreboard （read to get data for debug,and write to
                                      clear halt thread)   0x6:TDR (only in SMF)   0x7:ETR0(only in SMF)   0x8:ETR1(only
                                      in SMF)   0x9:ARR (only in SMF)   others:reservedNOTE：memory not support CSR write
                                      oper ation when the thread is running */
        unsigned int smeg1IndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smeg1IndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smeg1IndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_INDRECT_CTRL_U;

/* **
 * Union name :    SMEG1_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmeg1IndrectTimeout {
    struct tagStSmeg1IndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1IndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smeg1IndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMEG1_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmeg1IndrectData {
    struct tagStSmeg1IndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1IndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write:
                                       Software write data to these registes and then enable indirect access, logic will
                                       send these data to target.When operation read:  Logic write data to these
                                       registers and refresh xxx_indir_stat, software will get these data from target.
                                       */
#else
        unsigned int smeg1IndirData : 32;    /* * [31:0]It specifies the indirect access data:When operation write:
                                          Software write data to these registes and then enable indirect access, logic will
                                          send these data to target.When operation read:  Logic write data to these
                                          registers and refresh xxx_indir_stat, software will get these data from target.
                                          */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_INDRECT_DATA_U;

/* **
* Union name :    SMEG1_CNT_CFG
* @brief               SMEG1 counter configuration register.  This register is used for debug or for statistics
collection

* Description:
*/
typedef union tagUnSmeg1CntCfg {
    struct tagStSmeg1CntCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 19;   /* * [31:13]SMEG1 has four counters to count various events generated in the
                                  infrastructure or in the engines.  For the engines, the events can also be counted for a
                                  specif ic instance, as programmed in the smeg1_cnt_match_id register. */
        unsigned int cnt3Sel : 1;     /* * [12:12]0: SEND1:ENGINE_EVENT[3] */
        unsigned int cnt2Sel : 1;     /* * [11:11]0:FINISH1:ENGINE_EVENT[2] */
        unsigned int cnt1Sel : 2;     /* * [10:9]00:WAKEUP01:SLEEP10:ENGINE_LD_ST11:ENGINE_EVENT[1] */
        unsigned int cnt0Sel : 1;     /* * [8:8]0:INSTALL1:ENGINE_EVENT[0] */
        unsigned int cnt3MatchEn : 1; /* * [7:7]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                   counter will count the event for every instance.               1: count for specific
                                   instanc e only                                0: count for every instance */
        unsigned int cnt2MatchEn : 1; /* * [6:6]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                   counter will count the event for every instance.               1: count for specific
                                   instanc e only                                0: count for every instance */
        unsigned int cnt1MatchEn : 1; /* * [5:5]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                   counter will count the event for every instance.               1: count for specific
                                   instanc e only                                0: count for every instance */
        unsigned int cnt0MatchEn : 1; /* * [4:4]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                   counter will count the event for every instance.               1: count for specific
                                   instanc e only                                0: count for every instance */
        unsigned int cnt3Enable : 1;  /* * [3:3]1: counter3 is enabled            0: counter3 is disabled */
        unsigned int cnt2Enable : 1;  /* * [2:2]1: counter2 is enabled            0: counter2 is disabled */
        unsigned int cnt1Enable : 1;  /* * [1:1]1: counter1 is enabled            0: counter1 is disabled */
        unsigned int cnt0Enable : 1;  /* * [0:0]1: counter0 is enabled            0: counter0 is disabled */
#else
        unsigned int cnt0Enable : 1;         /* * [0:0]1: counter0 is enabled            0: counter0 is disabled */
        unsigned int cnt1Enable : 1;         /* * [1:1]1: counter1 is enabled            0: counter1 is disabled */
        unsigned int cnt2Enable : 1;         /* * [2:2]1: counter2 is enabled            0: counter2 is disabled */
        unsigned int cnt3Enable : 1;         /* * [3:3]1: counter3 is enabled            0: counter3 is disabled */
        unsigned int cnt0MatchEn : 1;      /* * [4:4]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                        counter will count the event for every instance.               1: count for specific
                                        instanc e only                                0: count for every instance */
        unsigned int cnt1MatchEn : 1;      /* * [5:5]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                        counter will count the event for every instance.               1: count for specific
                                        instanc e only                                0: count for every instance */
        unsigned int cnt2MatchEn : 1;      /* * [6:6]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                        counter will count the event for every instance.               1: count for specific
                                        instanc e only                                0: count for every instance */
        unsigned int cnt3MatchEn : 1;      /* * [7:7]Count for a 'specific Instance ID'. if this bit is not enabled, the
                                        counter will count the event for every instance.               1: count for specific
                                        instanc e only                                0: count for every instance */
        unsigned int cnt0Sel : 1;          /* * [8:8]0:INSTALL1:ENGINE_EVENT[0] */
        unsigned int cnt1Sel : 2;          /* * [10:9]00:WAKEUP01:SLEEP10:ENGINE_LD_ST11:ENGINE_EVENT[1] */
        unsigned int cnt2Sel : 1;          /* * [11:11]0:FINISH1:ENGINE_EVENT[2] */
        unsigned int cnt3Sel : 1;          /* * [12:12]0: SEND1:ENGINE_EVENT[3] */
        unsigned int reserved : 19;        /* * [31:13]SMEG1 has four counters to count various events generated in the
                                       infrastructure or in the engines.  For the engines, the events can also be counted for a
                                       specif ic instance, as programmed in the smeg1_cnt_match_id register. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_CNT_CFG_U;

/* **
* Union name :    SMEG1_CNT_MATCH_ID
* @brief               This register is used to configure Instance IDs for all four counters.  This can be used for
debug or for performance analysis.

* Description:
*/
typedef union tagUnSmeg1CntMatchId {
    struct tagStSmeg1CntMatchId {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 8;    /* * [31:24]reserved */
        unsigned int cnt3MatchId : 6; /* * [23:18]Instance ID for counter 3 */
        unsigned int cnt2MatchId : 6; /* * [17:12]Instance ID for counter 2 */
        unsigned int cnt1MatchId : 6; /* * [11:6]Instance ID for counter 1 */
        unsigned int cnt0MatchId : 6; /* * [5:0]Instance ID for counter 0 */
#else
        unsigned int cnt0MatchId : 6;      /* * [5:0]Instance ID for counter 0 */
        unsigned int cnt1MatchId : 6;      /* * [11:6]Instance ID for counter 1 */
        unsigned int cnt2MatchId : 6;      /* * [17:12]Instance ID for counter 2 */
        unsigned int cnt3MatchId : 6;      /* * [23:18]Instance ID for counter 3 */
        unsigned int reserved : 8;         /* * [31:24]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_CNT_MATCH_ID_U;

/* **
* Union name :    SMEG1_CNT0
* @brief               This smmeg1 counter0 register is a statistics counter that counts API install and engine event0

* Description:
*/
typedef union tagUnSmeg1Cnt0 {
    struct tagStSmeg1Cnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
        unsigned long long smeg1Cnt0 : 48; /* * [47:0]depending on the configuration this counter counts command
                                            * install, or engine event 0.  This can also be programmed to count only for
                                            * a specific instance
                                            */
#else
        unsigned long long smeg1Cnt0 : 48; /* * [47:0]depending on the configuration this counter counts command
                                            * install, or engine event 0.  This can also be programmed to count only for
                                            * a specific instance
                                            */
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMEG1_CNT0_U;

/* **
* Union name :    SMEG1_CNT1
* @brief               This smeg1 counter1 register is a statistics counter that counts load, store, sleep, wakeup, and
engine event 1

* Description:
*/
typedef union tagUnSmeg1Cnt1 {
    struct tagStSmeg1Cnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
        unsigned long long smeg1Cnt1 : 48; /* * [47:0]depending on the configuration this counter counts thread
                                 prel-oadstore, sleep, wakeup, or engine event 1.  This can also be programmed to count
                                 only for a spec ific instance */
#else
        unsigned long long smeg1Cnt1 : 48; /* * [47:0]depending on the configuration this counter counts thread
                                 prel-oadstore, sleep, wakeup, or engine event 1.  This can also be programmed to count
                                 only for a spec ific instance */
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMEG1_CNT1_U;

/* **
* Union name :    SMEG1_CNT2
* @brief               This smeg1 counter1 register is a statistics counter that counts 'finish' or engine event 2

* Description:
*/
typedef union tagUnSmeg1Cnt2 {
    struct tagStSmeg1Cnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
        unsigned long long smeg1Cnt2 : 48; /* * [47:0]depending on the configuration this counter counts thread
                                            * terminate, or engine event 2.  This can also be programmed to count only
                                            * for a specific instance
                                            */
#else
        unsigned long long smeg1Cnt2 : 48; /* * [47:0]depending on the configuration this counter counts thread
                                            * terminate, or engine event 2.  This can also be programmed to count only
                                            * for a specific instance
                                            */
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMEG1_CNT2_U;

/* **
* Union name :    SMEG1_CNT3
* @brief               This smeg1 counter3 register is a statistics counter that counts 'send' and engine event 3

* Description:
*/
typedef union tagUnSmeg1Cnt3 {
    struct tagStSmeg1Cnt3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
        unsigned long long smeg1Cnt3 : 48; /* * [47:0]depending on the configuration this counter counts message send to
                                            * smit , or engine event 3.  This can also be programmed to count only for a
                                            * specific instance
                                            */
#else
        unsigned long long smeg1Cnt3 : 48; /* * [47:0]depending on the configuration this counter counts message send to
                                            * smit , or engine event 3.  This can also be programmed to count only for a
                                            * specific instance
                                            */
        unsigned long long reserved : 16;  /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMEG1_CNT3_U;

/* **
* Union name :    SMEG1_TCD_CTP
* @brief               This is  the SMEG1 thread TCD register.  This register contains the read  data that  comes from
the TCD.

* Description:
*/
typedef union tagUnSmeg1TcdCtp {
    struct tagStSmeg1TcdCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 8; /* * [31:24]reserved. */
        unsigned int ctp : 24;     /* * [23:0][23:18] : instance id [17:15]: error response type[14] : rd2_etr1_id[13] :
                               rd2_etr0_id[12] : rd1_etr1_id[11] : rd1_etr0_id [10] : o-bit  [9:5] : engine id[4] : gpr1 id
                               in second issue[3] : gpr0 id in second issue[2] : dual issue [1] : gpr1 id in first issue [0]
                               : gpr0 id in first issue
                                */
#else
        unsigned int ctp : 24;     /* * [23:0][23:18] : instance id [17:15]: error response type[14] : rd2_etr1_id[13] :
                               rd2_etr0_id[12] : rd1_etr1_id[11] : rd1_etr0_id [10] : o-bit  [9:5] : engine id[4] : gpr1 id
                               in second issue[3] : gpr0 id in second issue[2] : dual issue [1] : gpr1 id in first issue [0]
                               : gpr0 id in first issue
                                */
        unsigned int reserved : 8; /* * [31:24]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TCD_CTP_U;

/* **
* Union name :    SMEG1_RUNAWAY_THD_CTP
* @brief               Each bit represents a runaway thread.  When a thread runs for more than a sampling time, it is
considered a runaway thread.  Bit63 logs runaway errors for the t hread 63, and bit0 logs the error for the thread 0
respectively.
* Description:
*/
typedef union tagUnSmeg1RunawayThdCtp {
    struct tagStSmeg1RunawayThdCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int ctp : 32; /* * [31:0]1: This thread is active for a very long time (>sample period). No new issue
                           for this thread.                                                             0: nor mal
                           operation                                            If configured, this register also can be
                           used for active thread ctp.
                            */
#else
        unsigned int ctp : 32; /* * [31:0]1: This thread is active for a very long time (>sample period). No new issue
                           for this thread.                                                             0: nor mal
                           operation                                            If configured, this register also can be
                           used for active thread ctp.
                            */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_RUNAWAY_THD_CTP_U;

/* **
 * Union name :    SMEG1_CTP0
 * @brief               This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register.
 * Description:
 */
typedef union tagUnSmeg1Ctp0 {
    struct tagStSmeg1Ctp0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 8;          /* * [63:56]reserved. */
        unsigned long long tcd : 24;              /* * [55:32]TCD ctp registers */
        unsigned long long activeRunawayThd : 32; /* * [31:0]32thread scoreboard active */
#else
        unsigned long long activeRunawayThd : 32; /* * [31:0]32thread scoreboard active */
        unsigned long long tcd : 24;              /* * [55:32]TCD ctp registers */
        unsigned long long reserved : 8;          /* * [63:56]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMEG1_CTP0_U;

/* **
 * Union name :    SMEG1_CTP1
 * @brief               This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register.
 * Description:
 */
typedef union tagUnSmeg1Ctp1 {
    struct tagStSmeg1Ctp1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 20;      /* * [63:44]reserved */
        unsigned long long smeg1Internal : 44; /* * [43:0][43:41]     fifoD_ctl_credit(6), [40:38] fifoD_data_credit(6)
                                     [37]       fifo a_sop(0)                                          [36] fifob_sop(0)
                                     [35]       fifoc_sop(0) [34]       fifoa_eop(0) [33]       fifob_eop(0) [32]
                                     fifoc_eop(0)                                                             [31]
                                     riq_valid(0),                                        [30] iiq_valid(0), [29]
                                     fifoa_allocated(0),                                   [28] fifob_allocated(0), [27]
                                     fifoc_allocated(0),                                 [26]       abuf_afifo_valid(0),
                                     [25] fifob_prestore(0),                                [24] fifoc_prestore(0),
                                     [23:20]    fairness_count(0), [19:17]    reserved (0)[16]       fifoe_empty(1)[15]
                                     fifoe_full (0)                                              [14] fifoa_empty(1)
                                                                        [13]       fifoa_full (0) [12] fifob_empty(1)
                                                    [11]       fifob_full(0) [10]       fifoC_empty(1), [9]
                                          fifoc_full(0)                                                       [8:2]
                                     available_thd_id  The default value of availble_thd_id in SML and SMF is dif
                                     ferent, SML is 14 in Dec; SMF is 30 in Dec. [1]  allocate_available(1) [0]
                                     resp_thd_free (0)The default value of smeg1_internal in SMF is 0x0d800001547a; in
                                     SML is :0x0d800001543a;
                                      */
#else
        unsigned long long smeg1Internal : 44; /* * [43:0][43:41]     fifoD_ctl_credit(6), [40:38] fifoD_data_credit(6)
                                     [37]       fifo a_sop(0)                                          [36] fifob_sop(0)
                                     [35]       fifoc_sop(0) [34]       fifoa_eop(0) [33]       fifob_eop(0) [32]
                                     fifoc_eop(0)                                                             [31]
                                     riq_valid(0),                                        [30] iiq_valid(0), [29]
                                     fifoa_allocated(0),                                   [28] fifob_allocated(0), [27]
                                     fifoc_allocated(0),                                 [26]       abuf_afifo_valid(0),
                                     [25] fifob_prestore(0),                                [24] fifoc_prestore(0),
                                     [23:20]    fairness_count(0), [19:17]    reserved (0)[16]       fifoe_empty(1)[15]
                                     fifoe_full (0)                                              [14] fifoa_empty(1)
                                                                        [13]       fifoa_full (0) [12] fifob_empty(1)
                                                    [11]       fifob_full(0) [10]       fifoC_empty(1), [9]
                                          fifoc_full(0)                                                       [8:2]
                                     available_thd_id  The default value of availble_thd_id in SML and SMF is dif
                                     ferent, SML is 14 in Dec; SMF is 30 in Dec. [1]  allocate_available(1) [0]
                                     resp_thd_free (0)The default value of smeg1_internal in SMF is 0x0d800001547a; in
                                     SML is :0x0d800001543a;
                                      */
        unsigned long long reserved : 20;      /* * [63:44]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMEG1_CTP1_U;

/* **
 * Union name :    SMEG1_CTP2
 * @brief               This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register.
 * Description:
 */
typedef union tagUnSmeg1Ctp2 {
    struct tagStSmeg1Ctp2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int wtRunaway : 32; /* * [31:0]thread runaway counter has overflow, and thread is in the status of
                                      * waiting new issued of this thread or terminate of this thread;
                                      */
#else
        unsigned int wtRunaway : 32;      /* * [31:0]thread runaway counter has overflow, and thread is in the status of
                                           * waiting new issued of this thread or terminate of this thread;
                                           */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_CTP2_U;

/* **
 * Union name :    SMEG1_TMT_EXT_CFG
 * @brief               TIMER engine control info
 * Description:
 */
typedef union tagUnSmeg1TmtExtCfg {
    struct tagStSmeg1TmtExtCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smeg1TmtExtCfg : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual
                                      entry size and cache line size.value indcates:00: actual size/cache line szie =
                                      1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11:
                                      actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 31Bit [29:28]: entry
                                      30Bit [27: 26]: entry 29Bit [25:24]: entry 28Bit [23:22]: entry 27Bit [21:20]:
                                      entry 26Bit [19:18]: entry 25Bit [17:16]: entry 24Bit [15:14]: entry 23Bit
                                      [13:12]: entry 22 Bit [11:10]: entry 21Bit [9:8]  : entry 20Bit [7:6]  : entry
                                      19Bit [5:4]  : entry 18Bit [3:2]  : entry 17Bit [1:0]  : entry 16
                                       */
#else
        unsigned int smeg1TmtExtCfg : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual
                                      entry size and cache line size.value indcates:00: actual size/cache line szie =
                                      1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11:
                                      actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 31Bit [29:28]: entry
                                      30Bit [27: 26]: entry 29Bit [25:24]: entry 28Bit [23:22]: entry 27Bit [21:20]:
                                      entry 26Bit [19:18]: entry 25Bit [17:16]: entry 24Bit [15:14]: entry 23Bit
                                      [13:12]: entry 22 Bit [11:10]: entry 21Bit [9:8]  : entry 20Bit [7:6]  : entry
                                      19Bit [5:4]  : entry 18Bit [3:2]  : entry 17Bit [1:0]  : entry 16
                                       */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_TMT_EXT_CFG_U;

/* **
* Union name :    SMEG1_MEM_ECC_ERR_CTP
* @brief               ecc ERR ADDR; CAPTURE the last err addr;only valid when the ECC interrupt is reported;

* Description:
*/
typedef union tagUnSmeg1MemEccErrCtp {
    struct tagStSmeg1MemEccErrCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 18; /* * [31:14]reserved */
        unsigned int addr : 6;      /* * [13:8]err_addr:for fidr: err instance ID;for other mem: [13:9]-error thread ID,
                                     * bit[8]-err mem ID;
                                     */
        unsigned int flag : 8; /* * [7:0]flag to indicate which memory the err_addr is:7 - fidr6 - gpr05 - gpr14 - etr03
                                * - etr12 - esr1 - tdr0 - arr
                                */
#else
        unsigned int flag : 8; /* * [7:0]flag to indicate which memory the err_addr is:7 - fidr6 - gpr05 - gpr14 - etr03
                                * - etr12 - esr1 - tdr0 - arr
                                */
        unsigned int addr : 6; /* * [13:8]err_addr:for fidr: err instance ID;for other mem: [13:9]-error thread ID,
                                * bit[8]-err mem ID;
                                */
        unsigned int reserved : 18; /* * [31:14]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_MEM_ECC_ERR_CTP_U;

/* **
 * Union name :    SMMC_CACHE_RESOURCE_CTP
 * @brief               SMMC WQE Cache resource counter
 * Description:
 */
typedef union tagUnSmmcCacheResourceCtp {
    struct tagStSmmcCacheResourceCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 2; /* * [31:30]reserved */
        unsigned int rqCnt : 14; /* * [29:16]SMMC RQ WQE Cache resource counter, This field indicate cache line number
                                  * has been used.
                                  */
        unsigned int reserved1 : 2; /* * [15:14]reserved */
        unsigned int sqCnt : 14;    /* * [13:0]SMMC SQ WQE Cache resource counter, This field indicate cache line number
                                     * has been used.
                                     */
#else
        unsigned int sqCnt : 14;    /* * [13:0]SMMC SQ WQE Cache resource counter, This field indicate cache line number
                                     * has been used.
                                     */
        unsigned int reserved1 : 2; /* * [15:14]reserved */
        unsigned int rqCnt : 14; /* * [29:16]SMMC RQ WQE Cache resource counter, This field indicate cache line number
                                  * has been used.
                                  */
        unsigned int reserved0 : 2;        /* * [31:30]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_CACHE_RESOURCE_CTP_U;

/* **
 * Union name :    SMEG1_SYNC_API_CFG
 * @brief               SYNC_API configuration register
 * Description:
 */
typedef union tagUnSmeg1SyncApiCfg {
    struct tagStSmeg1SyncApiCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 22;       /* * [31:10]reserved */
        unsigned int syncCntThreshold : 2; /* * [9:8]The number of sync API allowed to waiting for getting lock must be
                                            * equal or less than this threshold.0: max number is 4;1~3: max number;
                                            */
        unsigned int reserved1 : 2;        /* * [7:6]reserved */
        unsigned int snapshotEngEn : 1;    /* * [5:5]enable snapshot based engine ID0: disable1: enable */
        unsigned int snapshotEngId : 5;    /* * [4:0]SYNC_API snapshot engine IDdefault to timer engine ID. */
#else
        unsigned int snapshotEngId : 5;    /* * [4:0]SYNC_API snapshot engine IDdefault to timer engine ID. */
        unsigned int snapshotEngEn : 1;    /* * [5:5]enable snapshot based engine ID0: disable1: enable */
        unsigned int reserved1 : 2;        /* * [7:6]reserved */
        unsigned int syncCntThreshold : 2; /* * [9:8]The number of sync API allowed to waiting for getting lock must be
                                            * equal or less than this threshold.0: max number is 4;1~3: max number;
                                            */
        unsigned int reserved0 : 22;       /* * [31:10]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMEG1_SYNC_API_CFG_U;

/* **
 * Union name :    SMEG1_CUR_TIMESTAMP_US
 * @brief               Current timestamp (us)
 * Description:
 */
typedef union tagUnSmeg1CurTimestampUs {
    struct tagStSmeg1CurTimestampUs {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 15; /* * [63:49]reserved. */
        unsigned long long ctp : 49;      /* * [48:0]Current timestamp (us) */
#else
        unsigned long long ctp : 49;       /* * [48:0]Current timestamp (us) */
        unsigned long long reserved : 15;  /* * [63:49]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMEG1_CUR_TIMESTAMP_US_U;


/* **
 * Union name :    SMIT_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmitVersion {
    struct tagStSmitVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smitVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smitVersion : 32;     /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_VERSION_U;

/* **
* Union name :    SMIT_CFG
* @brief               This is the Smart Memory Infra Transmission (SMIT) module configuration register.  The software
use this register for debug.

* Description:
*/
typedef union tagUnSmitCfg {
    struct tagStSmitCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 12;       /* * [31:20]reserved */
        unsigned int rpUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when
                                        posedge of this bit is detected; After Err injection start, err is injected when
                                        a memory read is is sued to the memory. Enable memory check, when use this err
                                        inection function. */
        unsigned int rpCrtErrInjReq : 1;   /* * [18:18]ECC crt err injection requestion;err injection start when posedge
                                        of this bit is detected; After Err injection start, err is injected when a memory
                                        read is issu ed to the memory.Enable memory check, when use this err inection
                                        function. */
        unsigned int memPbChkEn : 1; /* * [17:17]memory check enable.1'b0:disable all memories check.1'b1:enable all
                                      * memories check.
                                      */
        unsigned int memRet1n : 1;   /* * [16:16]control of memory pin RET1N */
        unsigned int tpRamTmod : 8;  /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                      * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                      */
        unsigned int reserved1 : 7;  /* * [7:1] */
        unsigned int disOder : 1;    /* * [0:0]Ordering queue enable configuration.this is for debug . Software can
                                  disable SMIT ordering queue function via this field . Hw will ignore O-bit inside API w
                                  hen software set this field. 1 : disable ordering transmission .0: enable ordering
                                  transmission.Note:only used for debug,users should know the api counts before
                                   config this bit. */
#else
        unsigned int disOder : 1;    /* * [0:0]Ordering queue enable configuration.this is for debug . Software can
                                  disable SMIT ordering queue function via this field . Hw will ignore O-bit inside API w
                                  hen software set this field. 1 : disable ordering transmission .0: enable ordering
                                  transmission.Note:only used for debug,users should know the api counts before
                                   config this bit. */
        unsigned int reserved1 : 7;  /* * [7:1] */
        unsigned int tpRamTmod : 8;  /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                      * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                      */
        unsigned int memRet1n : 1;   /* * [16:16]control of memory pin RET1N */
        unsigned int memPbChkEn : 1; /* * [17:17]memory check enable.1'b0:disable all memories check.1'b1:enable all
                                      * memories check.
                                      */
        unsigned int rpCrtErrInjReq : 1;   /* * [18:18]ECC crt err injection requestion;err injection start when posedge
                                        of this bit is detected; After Err injection start, err is injected when a memory
                                        read is issu ed to the memory.Enable memory check, when use this err inection
                                        function. */
        unsigned int rpUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when
                                        posedge of this bit is detected; After Err injection start, err is injected when
                                        a memory read is is sued to the memory. Enable memory check, when use this err
                                        inection function. */
        unsigned int reserved0 : 12;       /* * [31:20]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_CFG_U;

/* **
 * Union name :    SMIT_INT_VECTOR
 * @brief               SMIT interrupt vector
 * Description:
 */
typedef union tagUnSmitIntVector {
    struct tagStSmitIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                     * register0:interrupt disable1:interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;       /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                        * register0:interrupt disable1:interrupt enable
                                        */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_INT_VECTOR_U;

/* **
 * Union name :    SMIT_INT
 * @brief               SMIT interrupt status vector
 * Description:
 */
typedef union tagUnSmitInt {
    struct tagStSmitInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 13;     /* * [15:3]reserved */
        unsigned int intData : 3;       /* * [2:0]interrupt masked field,it is the collection of the error bits from the
                                     corresponding error registers on the sheet1 : SMIT memory (TMDR/TMHR/TMNHR) parity error
                                     deteced . 0 : No SMIT memory parity error deteced. */
#else
        unsigned int intData : 3;   /* * [2:0]interrupt masked field,it is the collection of the error bits from the
                                 corresponding error registers on the sheet1 : SMIT memory (TMDR/TMHR/TMNHR) parity error
                                 deteced . 0 : No SMIT memory parity error deteced. */
        unsigned int reserved : 13; /* * [15:3]reserved */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_INT_U;

/* **
 * Union name :    SMIT_INT_MASK
 * @brief               SMIT interrupt mask vector
 * Description:
 */
typedef union tagUnSmitIntMask {
    struct tagStSmitIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 13;     /* * [15:3]reserved */
        unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 13;      /* * [15:3]reserved */
        unsigned int programCsrId : 16;  /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                          * of CSR modules) asked for the interrupt
                                          */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_INT_MASK_U;

/* **
 * Union name :    SMIT_ERR_PRTY
 * @brief               RSV
 * Description:
 */
typedef union tagUnSmitErrPrty {
    struct tagStSmitErrPrty {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;       /* * [31:2]RSV */
        unsigned int multiErrorBit : 1; /* * [1:1]RSV */
        unsigned int errorBit : 1;      /* * [0:0]RSV */
#else
        unsigned int errorBit : 1;       /* * [0:0]RSV */
        unsigned int multiErrorBit : 1;  /* * [1:1]RSV */
        unsigned int sticky : 30;        /* * [31:2]RSV */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_ERR_PRTY_U;

/* **
 * Union name :    SMIT_MEM_ECC_CRT_ERR
 * @brief               tmdr ecc correctable err
 * Description:
 */
typedef union tagUnSmitMemEccCrtErr {
    struct tagStSmitMemEccCrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is
                                    offbit11:4: err tmdr addressbit3:0: err_tmdr_id    bit3 - tmdr3 error detected    bit2 -
                                    tmdr2 error detected    bit1 - tmdr1 error detected    bit0 - tmdr0 error detected */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;       /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1;  /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;        /* * [31:2]captures error state of the first error, capture even if mask is
                                     offbit11:4: err tmdr addressbit3:0: err_tmdr_id    bit3 - tmdr3 error detected    bit2 -
                                     tmdr2 error detected    bit1 - tmdr1 error detected    bit0 - tmdr0 error detected */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_MEM_ECC_CRT_ERR_U;

/* **
 * Union name :    SMIT_MEM_ECC_UNCRT_ERR
 * @brief               tmdr ecc uncorrectable err
 * Description:
 */
typedef union tagUnSmitMemEccUncrtErr {
    struct tagStSmitMemEccUncrtErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;       /* * [31:2]captures error state of the first error, capture even if mask is
                                    offbit11:4: err tmdr addressbit3:0: err_tmdr_id    bit3 - tmdr3 error detected    bit2 -
                                    tmdr2 error detected    bit1 - tmdr1 error detected    bit0 - tmdr0 error detected */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;       /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1;  /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30;        /* * [31:2]captures error state of the first error, capture even if mask is
                                     offbit11:4: err tmdr addressbit3:0: err_tmdr_id    bit3 - tmdr3 error detected    bit2 -
                                     tmdr2 error detected    bit1 - tmdr1 error detected    bit0 - tmdr0 error detected */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_MEM_ECC_UNCRT_ERR_U;

/* **
 * Union name :    SMIT_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmitIndrectCtrl {
    struct tagStSmitIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smitIndirVld : 1;   /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
        unsigned int smitIndirMode : 1;  /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smitIndirStat : 2;  /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smitIndirTab : 4;   /* * [27:24]It specifies memory group or table.    0x0:TMHR   0x1:TMNHR
                                      0x2:TMLIST (only support read op)   0x3:TMCD (only support read op)   0x4:TMDR0
                                      0x5:TMDR1 0x6: TMDR2   0x7:TMDR3   others:reserved */
        unsigned int smitIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address
                                     in one group or internal address of the table.1.bit[11:3] memory address    in SML:
                                     TMDR bit[10:3] valid     TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid   in SMF:     TMDR
                                     bit[11:3] valid     TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid2.bit[2:0] word select:
                                     0~3: reserved,   0x4:mem_dat[127:96]   0x5:mem_dat[95:64]   0x6:mem_dat[63:32]
                                     0x7:mem_dat[31:0]Note 1: for accessing tmhr/ tmnhr/ tmlist/ tmcd,bit[2:0] shoul d
                                     be 0x7.; */
#else
        unsigned int smitIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address
                                     in one group or internal address of the table.1.bit[11:3] memory address    in SML:
                                     TMDR bit[10:3] valid     TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid   in SMF:     TMDR
                                     bit[11:3] valid     TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid2.bit[2:0] word select:
                                     0~3: reserved,   0x4:mem_dat[127:96]   0x5:mem_dat[95:64]   0x6:mem_dat[63:32]
                                     0x7:mem_dat[31:0]Note 1: for accessing tmhr/ tmnhr/ tmlist/ tmcd,bit[2:0] shoul d
                                     be 0x7.; */
        unsigned int smitIndirTab : 4;   /* * [27:24]It specifies memory group or table.    0x0:TMHR   0x1:TMNHR
                                      0x2:TMLIST (only support read op)   0x3:TMCD (only support read op)   0x4:TMDR0
                                      0x5:TMDR1 0x6: TMDR2   0x7:TMDR3   others:reserved */
        unsigned int smitIndirStat : 2;  /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smitIndirMode : 1;  /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smitIndirVld : 1;   /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_INDRECT_CTRL_U;

/* **
 * Union name :    SMIT_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmitIndrectTimeout {
    struct tagStSmitIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smitIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smitIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMIT_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmitIndrectData {
    struct tagStSmitIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smitIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#else
        unsigned int smitIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMIT_INDRECT_DATA_U;


/* **
 * Union name :    SMLC_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmlcVersion {
    struct tagStSmlcVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smlcVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smlcVersion : 32;   /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_VERSION_U;

/* **
 * Union name :    SMLC_CFG0
 * @brief               Smart Memory Lock Cache Controller (SMLC)  configuration 0.
 * Description:
 */
typedef union tagUnSmlcCfg0 {
    struct tagStSmlcCfg0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 8; /* * [31:24]reserved */
        unsigned int memRet1n : 1;  /* * [23:23]control of memory pin RET1N */
        unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                     * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                     * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                     */
        unsigned int reserved1 : 5; /* * [7:3]reserved */
        unsigned int smlcUncrtErrInj : 1; /* * [2:2]smlc ECC un-corrected err injection requestion;err injection start
                                       when posedge of this bit is detected; After Err injection start, err is injected
                                       when a memor y read is issued to the memory. */
        unsigned int smlcCrtErrInj : 1;   /* * [1:1]smlc ECC corrected err injection requestion;err injection start when
                                       posedge of this bit is detected; After Err injection start, err is injected when a
                                       memory r ead is issued to the memory. */
        unsigned int smlcEccChkEn : 1;    /* * [0:0]whether enable ECC check.0:disable;1:enable. */
#else
        unsigned int smlcEccChkEn : 1;   /* * [0:0]whether enable ECC check.0:disable;1:enable. */
        unsigned int smlcCrtErrInj : 1;  /* * [1:1]smlc ECC corrected err injection requestion;err injection start when
                                      posedge of this bit is detected; After Err injection start, err is injected when a
                                      memory r ead is issued to the memory. */
        unsigned int smlcUncrtErrInj : 1; /* * [2:2]smlc ECC un-corrected err injection requestion;err injection start
                                       when posedge of this bit is detected; After Err injection start, err is injected
                                       when a memor y read is issued to the memory. */
        unsigned int reserved1 : 5;       /* * [7:3]reserved */
        unsigned int tpRamTmod : 8;       /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                           * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                           */
        unsigned int spRamTmod : 7;     /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                         * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                         */
        unsigned int memRet1n : 1;      /* * [23:23]control of memory pin RET1N */
        unsigned int reserved0 : 8;     /* * [31:24]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_CFG0_U;

/* **
 * Union name :    SMLC_CFG1
 * @brief               Smart Memory Lock Cache Controller (SMLC)  configuration 1.
 * Description:
 */
typedef union tagUnSmlcCfg1 {
    struct tagStSmlcCfg1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int bypassCd310 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data31~cache data0.0:not
                                        * bypass;1:bypass.In this situation, the cache data is always invalid.
                                        */
#else
        unsigned int bypassCd310 : 32;  /* * [31:0]whether bypass cache data.Bit31~bit0:cache data31~cache data0.0:not
                                         * bypass;1:bypass.In this situation, the cache data is always invalid.
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_CFG1_U;

/* **
 * Union name :    SMLC_CFG2
 * @brief               Smart Memory Lock Cache Controller (SMLC)  configuration 2.
 * Description:
 */
typedef union tagUnSmlcCfg2 {
    struct tagStSmlcCfg2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int bypassCd6332 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data63~cache data32.0:not
                                         * bypass;1:bypass.In this situation, the cache data is always invalid.
                                         */
#else
        unsigned int bypassCd6332 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data63~cache data32.0:not
                                         * bypass;1:bypass.In this situation, the cache data is always invalid.
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_CFG2_U;

/* **
 * Union name :    SMLC_INT_VECTOR
 * @brief               Smart Memory Lock Cache Controller (SMLC) interrupt vector register
 * Description:
 */
typedef union tagUnSmlcIntVector {
    struct tagStSmlcIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29] */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                     * register0:interrupt disable1:interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24;  /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                    that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                    dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;     /* * [26:24]reserved */
        unsigned int enable : 1;        /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                         * register0:interrupt disable1:interrupt enable
                                         */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_INT_VECTOR_U;

/* **
 * Union name :    SMLC_INT
 * @brief               Smart Memory Lock Cache Controller (SMLC) interrupt data register
 * Description:
 */
typedef union tagUnSmlcInt {
    struct tagStSmlcInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt.
                                         */
        unsigned int reserved : 14;     /* * [15:2]reserved */
        unsigned int intData : 2;       /* * [1:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 2;   /* * [1:0]interrupt masked field,it is the collection of the error bits from the
                                     * corresponding error registers on the sheet
                                     */
        unsigned int reserved : 14; /* * [15:2]reserved */
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt.
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_INT_U;

/* **
 * Union name :    SMLC_INT_MASK
 * @brief               Smart Memory Lock Cache Controller (SMLC) interrupt mask register.
 * Description:
 */
typedef union tagUnSmlcIntMask {
    struct tagStSmlcIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                    of CSR modules) asked for the interrupt.This register is used to mask any bits of
                                    the interru pt register. Software engineers can use this register to mask
                                    corresponding bits if they don not want these bits reporting to upper level.
                                     */
        unsigned int reserved : 14;     /* * [15:2] */
        unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 14;     /* * [15:2] */
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                    of CSR modules) asked for the interrupt.This register is used to mask any bits of
                                    the interru pt register. Software engineers can use this register to mask
                                    corresponding bits if they don not want these bits reporting to upper level.
                                     */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_INT_MASK_U;

/* **
 * Union name :    SMLC_SRF_OV_ERR
 * @brief               srf fifo overflow error.
 * Description:
 */
typedef union tagUnSmlcSrfOvErr {
    struct tagStSmlcSrfOvErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 29;     /* * [31:3]reserved. */
        unsigned int sticky : 1;        /* * [2:2]This field is fixed to be 0. */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 1;        /* * [2:2]This field is fixed to be 0. */
        unsigned int reserved : 29;     /* * [31:3]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_SRF_OV_ERR_U;

/* **
 * Union name :    SMLC_ECC_ERR
 * @brief               memory ecc error.
 * Description:
 */
typedef union tagUnSmlcEccErr {
    struct tagStSmlcEccErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 8;      /* * [31:24]reserved. */
        unsigned int pab2bEccMerr : 1;  /* * [23:23]pab memory 2bit ECC multi error; */
        unsigned int pab2bEccErr : 1;   /* * [22:22]pab memory 2bit ECC error; */
        unsigned int pab1bEccMerr : 1;  /* * [21:21]pab memory 1bit ECC multi error; */
        unsigned int pab1bEccErr : 1;   /* * [20:20]pab memory 1bit ECC error; */
        unsigned int cdb12bEccMerr : 1; /* * [19:19]cdb1 memory 2bit ECC multi error; */
        unsigned int cdb12bEccErr : 1;  /* * [18:18]cdb1 memory 2bit ECC error; */
        unsigned int cdb11bEccMerr : 1; /* * [17:17]cdb1 memory 1bit ECC multi error; */
        unsigned int cdb11bEccErr : 1;  /* * [16:16]cdb1 memory 1bit ECC error; */
        unsigned int cdb02bEccMerr : 1; /* * [15:15]cdb0 memory 2bit ECC multi error; */
        unsigned int cdb02bEccErr : 1;  /* * [14:14]cdb0 memory 2bit ECC error; */
        unsigned int cdb01bEccMerr : 1; /* * [13:13]cdb0 memory 1bit ECC multi error; */
        unsigned int cdb01bEccErr : 1;  /* * [12:12]cdb0 memory 1bit ECC error; */
        unsigned int stb2bEccMerr : 1;  /* * [11:11]stb memory 2bit ECC multi error; */
        unsigned int stb2bEccErr : 1;   /* * [10:10]stb memory 2bit ECC error; */
        unsigned int stb1bEccMerr : 1;  /* * [9:9]stb memory 1bit ECC multi error; */
        unsigned int stb1bEccErr : 1;   /* * [8:8]stb memory 1bit ECC error; */
        unsigned int bat2bEccMerr : 1;  /* * [7:7]bat memory 2bit ECC multi error; */
        unsigned int bat2bEccErr : 1;   /* * [6:6]bat memory 2bit ECC error; */
        unsigned int bat1bEccMerr : 1;  /* * [5:5]bat memory 1bit ECC multi error; */
        unsigned int bat1bEccErr : 1;   /* * [4:4]bat memory 1bit ECC error; */
        unsigned int fiar2bEccMerr : 1; /* * [3:3]fiar memory 2bit ECC multi error; */
        unsigned int fiar2bEccErr : 1;  /* * [2:2]fiar memory 2bit ECC error; */
        unsigned int fiar1bEccMerr : 1; /* * [1:1]fiar memory 1bit ECC multi error; */
        unsigned int fiar1bEccErr : 1;  /* * [0:0]fiar memory 1bit ECC error; */
#else
        unsigned int fiar1bEccErr : 1;  /* * [0:0]fiar memory 1bit ECC error; */
        unsigned int fiar1bEccMerr : 1; /* * [1:1]fiar memory 1bit ECC multi error; */
        unsigned int fiar2bEccErr : 1;  /* * [2:2]fiar memory 2bit ECC error; */
        unsigned int fiar2bEccMerr : 1; /* * [3:3]fiar memory 2bit ECC multi error; */
        unsigned int bat1bEccErr : 1;   /* * [4:4]bat memory 1bit ECC error; */
        unsigned int bat1bEccMerr : 1;  /* * [5:5]bat memory 1bit ECC multi error; */
        unsigned int bat2bEccErr : 1;   /* * [6:6]bat memory 2bit ECC error; */
        unsigned int bat2bEccMerr : 1;  /* * [7:7]bat memory 2bit ECC multi error; */
        unsigned int stb1bEccErr : 1;   /* * [8:8]stb memory 1bit ECC error; */
        unsigned int stb1bEccMerr : 1;  /* * [9:9]stb memory 1bit ECC multi error; */
        unsigned int stb2bEccErr : 1;   /* * [10:10]stb memory 2bit ECC error; */
        unsigned int stb2bEccMerr : 1;  /* * [11:11]stb memory 2bit ECC multi error; */
        unsigned int cdb01bEccErr : 1;  /* * [12:12]cdb0 memory 1bit ECC error; */
        unsigned int cdb01bEccMerr : 1; /* * [13:13]cdb0 memory 1bit ECC multi error; */
        unsigned int cdb02bEccErr : 1;  /* * [14:14]cdb0 memory 2bit ECC error; */
        unsigned int cdb02bEccMerr : 1; /* * [15:15]cdb0 memory 2bit ECC multi error; */
        unsigned int cdb11bEccErr : 1;  /* * [16:16]cdb1 memory 1bit ECC error; */
        unsigned int cdb11bEccMerr : 1; /* * [17:17]cdb1 memory 1bit ECC multi error; */
        unsigned int cdb12bEccErr : 1;  /* * [18:18]cdb1 memory 2bit ECC error; */
        unsigned int cdb12bEccMerr : 1; /* * [19:19]cdb1 memory 2bit ECC multi error; */
        unsigned int pab1bEccErr : 1;   /* * [20:20]pab memory 1bit ECC error; */
        unsigned int pab1bEccMerr : 1;  /* * [21:21]pab memory 1bit ECC multi error; */
        unsigned int pab2bEccErr : 1;   /* * [22:22]pab memory 2bit ECC error; */
        unsigned int pab2bEccMerr : 1;  /* * [23:23]pab memory 2bit ECC multi error; */
        unsigned int reserved : 8;      /* * [31:24]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_ECC_ERR_U;

/* **
 * Union name :    SMLC_ECC_ERRPR_MASK
 * @brief
 * Description:
 */
typedef union tagUnSmlcEccErrprMask {
    struct tagStSmlcEccErrprMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 20;        /* * [31:12]reserved. */
        unsigned int pab2bEccErrMask : 1;  /* * [11:11] */
        unsigned int pab1bEccErrMask : 1;  /* * [10:10] */
        unsigned int cdb12bEccErrMask : 1; /* * [9:9] */
        unsigned int cdb11bEccErrMask : 1; /* * [8:8] */
        unsigned int cdb02bEccErrMask : 1; /* * [7:7] */
        unsigned int cdb01bEccErrMask : 1; /* * [6:6] */
        unsigned int stb2bEccErrMask : 1;  /* * [5:5] */
        unsigned int stb1bEccErrMask : 1;  /* * [4:4] */
        unsigned int bat2bEccErrMask : 1;  /* * [3:3] */
        unsigned int bat1bEccErrMask : 1;  /* * [2:2] */
        unsigned int fiar2bEccErrMask : 1; /* * [1:1] */
        unsigned int fiar1bEccErrMask : 1; /* * [0:0] */
#else
        unsigned int fiar1bEccErrMask : 1; /* * [0:0] */
        unsigned int fiar2bEccErrMask : 1; /* * [1:1] */
        unsigned int bat1bEccErrMask : 1;  /* * [2:2] */
        unsigned int bat2bEccErrMask : 1;  /* * [3:3] */
        unsigned int stb1bEccErrMask : 1;  /* * [4:4] */
        unsigned int stb2bEccErrMask : 1;  /* * [5:5] */
        unsigned int cdb01bEccErrMask : 1; /* * [6:6] */
        unsigned int cdb02bEccErrMask : 1; /* * [7:7] */
        unsigned int cdb11bEccErrMask : 1; /* * [8:8] */
        unsigned int cdb12bEccErrMask : 1; /* * [9:9] */
        unsigned int pab1bEccErrMask : 1;  /* * [10:10] */
        unsigned int pab2bEccErrMask : 1;  /* * [11:11] */
        unsigned int reserved : 20;        /* * [31:12]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_ECC_ERRPR_MASK_U;

/* **
 * Union name :    SMLC_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmlcIndrectCtrl {
    struct tagStSmlcIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smlcIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                     invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                     indirect ac cess valid (software set). */
        unsigned int smlcIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smlcIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                         * done;2’b01: indirect access timeout;Others: reserved.
                                         */
        unsigned int
            smlcIndirTab : 7; /* * [27:21]It specifies memory group or table. 0:fiar;1:pab; SML:mem_index(18).
                           SMF:stateless and memory mode:     bankid(2),mem_index(19),reserved(88).     statefull mode
                           : bankid(2),
                           cid0(10),cid1(10),base_addr(56),pcie_template(6),host_id(2),base_addr_type(1),refill_len(6),refill_len_valid(1),o_bit(1),csize(2),vcache_base(10),b
                           size(2).2:stb;3:cdb0; 4:cdb1;5:rsv;6:rsv;7:rsv.8:req_list_info_0;  SML:
                           thread_id(4),base_sel(1),instance(6),mem_index(18),valid_cache_data(1),valid_list(1),hol
                           ding(1),sa_req(1),lha_req(1),28'b0.
                           SMF:thread_id(5),mem_index(56),valid_cache_data(1),valid_list(1),holding(1),sa_req(1),lha_req(1).mode(1),misc(1),mem(1),bat
                           _type(2),bpc(1),index_type(4),index_subtype(2),vf(10),ofst(6).9:req_list_info_1;……
                           SML时，只有 req_list_info_0~31有效。71:req_list_info_63;72:BAT pointer table.other value:
                           reserved. */
        unsigned int
            smlcIndirAddr : 21; /* * [20:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one
                            group or internal address of the table.14:5 - memory indexFor FIAR:   14:13 reserved, In
                            SMF:    12:8 is instance id;   7:5 is entry number in instance.   In SML:    12:7 is
                            instance id;   bit6 is entry number in instance.bit5 is RSV.For pab:(o nly support for CSR
                            read)   14:11 reserved,   10:6 thread ID, bit10 is RSV in SML.   5:3 reserved. 1个pab
                            entry的109bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个109bit，后续读此1
                            09bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先读地址bit[2:0]=7。   [2:0] word
                            select field.0x0:0x3 - reserved 0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:
                            data [31:0] For stb,(only support for CSR read)   14:11 reserved,   10:6 thread ID, bit10 is
                            RSV in SML.   [5:3]  16Byte data entry index in an entry; When 0x0, indi cate to read byte
                            enable.   [2:0]  word select field.0x0:0x2 - reserved 0x3:  data[159:128]0x4:
                            data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0]F or cdb0,(only support for
                            CSR read)   14:12 reserved,   11:6 list ID, bit11 is RSV in SML.   [5:3]  16Byte data entry
                            index in an entry;    [2:0]  word select f ield.0x0:0x2 - reserved0x3:  data[159:128](ECC
                            bit of 16B)0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0] For
                            cdb1,(only support for CSR re ad)   14:12 reserved,   11:6 list ID, bit11 is RSV in SML.
                            [5:3]  16Byte data entry index in an entry; When 0x0, indicate to read byte enable.   [2:0]
                            word s elect field.0x0: - reserved0x1:  data[223:192] 0x2:  data[191:160] 0x3:
                            data[159:128]0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0] For r
                            eq_list_info,(only support for CSR read)   14:3 reserved,   1个req_list_info
                            的94bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个94bit，后续读此94bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先
                            读地址bit[2:0]=7。   [2:0]  word select field.0x0:0x4 - reserved 0x5:  data[95:64]0x6:
                            data[63:32]0x7:  data[31:0]For BAT pointer table,   14:5 vf index.
                                                        */
#else
        unsigned int
            smlcIndirAddr : 21; /* * [20:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one
                            group or internal address of the table.14:5 - memory indexFor FIAR:   14:13 reserved, In
                            SMF:    12:8 is instance id;   7:5 is entry number in instance.   In SML:    12:7 is
                            instance id;   bit6 is entry number in instance.bit5 is RSV.For pab:(o nly support for CSR
                            read)   14:11 reserved,   10:6 thread ID, bit10 is RSV in SML.   5:3 reserved. 1个pab
                            entry的109bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个109bit，后续读此1
                            09bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先读地址bit[2:0]=7。   [2:0] word
                            select field.0x0:0x3 - reserved 0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:
                            data [31:0] For stb,(only support for CSR read)   14:11 reserved,   10:6 thread ID, bit10 is
                            RSV in SML.   [5:3]  16Byte data entry index in an entry; When 0x0, indi cate to read byte
                            enable.   [2:0]  word select field.0x0:0x2 - reserved 0x3:  data[159:128]0x4:
                            data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0]F or cdb0,(only support for
                            CSR read)   14:12 reserved,   11:6 list ID, bit11 is RSV in SML.   [5:3]  16Byte data entry
                            index in an entry;    [2:0]  word select f ield.0x0:0x2 - reserved0x3:  data[159:128](ECC
                            bit of 16B)0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0] For
                            cdb1,(only support for CSR re ad)   14:12 reserved,   11:6 list ID, bit11 is RSV in SML.
                            [5:3]  16Byte data entry index in an entry; When 0x0, indicate to read byte enable.   [2:0]
                            word s elect field.0x0: - reserved0x1:  data[223:192] 0x2:  data[191:160] 0x3:
                            data[159:128]0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0] For r
                            eq_list_info,(only support for CSR read)   14:3 reserved,   1个req_list_info
                            的94bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个94bit，后续读此94bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先
                            读地址bit[2:0]=7。   [2:0]  word select field.0x0:0x4 - reserved 0x5:  data[95:64]0x6:
                            data[63:32]0x7:  data[31:0]For BAT pointer table,   14:5 vf index.
                                                        */
        unsigned int
            smlcIndirTab : 7;           /* * [27:21]It specifies memory group or table. 0:fiar;1:pab; SML:mem_index(18).
                                     SMF:stateless and memory mode:     bankid(2),mem_index(19),reserved(88).     statefull mode
                                     : bankid(2),
                                     cid0(10),cid1(10),base_addr(56),pcie_template(6),host_id(2),base_addr_type(1),refill_len(6),refill_len_valid(1),o_bit(1),csize(2),vcache_base(10),b
                                     size(2).2:stb;3:cdb0; 4:cdb1;5:rsv;6:rsv;7:rsv.8:req_list_info_0;  SML:
                                     thread_id(4),base_sel(1),instance(6),mem_index(18),valid_cache_data(1),valid_list(1),hol
                                     ding(1),sa_req(1),lha_req(1),28'b0.
                                     SMF:thread_id(5),mem_index(56),valid_cache_data(1),valid_list(1),holding(1),sa_req(1),lha_req(1).mode(1),misc(1),mem(1),bat
                                     _type(2),bpc(1),index_type(4),index_subtype(2),vf(10),ofst(6).9:req_list_info_1;……
                                     SML时，只有 req_list_info_0~31有效。71:req_list_info_63;72:BAT pointer table.other value:
                                     reserved. */
        unsigned int smlcIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                         * done;2’b01: indirect access timeout;Others: reserved.
                                         */
        unsigned int smlcIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smlcIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                     invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                     indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_INDRECT_CTRL_U;

/* **
 * Union name :    SMLC_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmlcIndrectTimeout {
    struct tagStSmlcIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smlcIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smlcIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMLC_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmlcIndrectData {
    struct tagStSmlcIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smlcIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#else
        unsigned int smlcIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software
                                      write data to these registes and then enable indirect access, logic will send
                                      these data to target.When operation read:  Logic write data to these registers and
                                      refresh xxx_indir_stat, software will get these data from target.
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_INDRECT_DATA_U;

/* **
 * Union name :    SMLC_CNT0
 * @brief               Smart Memory Lock Cache Controller (SMLC) event counter0
 * Description:
 */
typedef union tagUnSmlcCnt0 {
    struct tagStSmlcCnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16; /* * [63:48]reserved. */
        unsigned long long smlcCnt0 : 48; /* * [47:0]Event counter 0, count SMLC event from cnt_cfg */
#else
        unsigned long long smlcCnt0 : 48;     /* * [47:0]Event counter 0, count SMLC event from cnt_cfg */
        unsigned long long reserved : 16;     /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMLC_CNT0_U;

/* **
 * Union name :    SMLC_CNT1
 * @brief               Smart Memory Lock Cache Controller (SMLC) event counter1
 * Description:
 */
typedef union tagUnSmlcCnt1 {
    struct tagStSmlcCnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16; /* * [63:48]reserved. */
        unsigned long long smlcCnt1 : 48; /* * [47:0]Event counter 1, count SMLC event from cnt_cfg */
#else
        unsigned long long smlcCnt1 : 48;     /* * [47:0]Event counter 1, count SMLC event from cnt_cfg */
        unsigned long long reserved : 16;     /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMLC_CNT1_U;

/* **
 * Union name :    SMLC_CNT2
 * @brief               Smart Memory Lock Cache Controller (SMLC) event counter2
 * Description:
 */
typedef union tagUnSmlcCnt2 {
    struct tagStSmlcCnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16; /* * [63:48]reserved. */
        unsigned long long smlcCnt2 : 48; /* * [47:0]Event counter 2, count SMLC event from cnt_cfg */
#else
        unsigned long long smlcCnt2 : 48;     /* * [47:0]Event counter 2, count SMLC event from cnt_cfg */
        unsigned long long reserved : 16;     /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMLC_CNT2_U;

/* **
 * Union name :    SMLC_CNT3
 * @brief               Smart Memory Lock Cache Controller (SMLC) event counter3
 * Description:
 */
typedef union tagUnSmlcCnt3 {
    struct tagStSmlcCnt3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16; /* * [63:48]reserved. */
        unsigned long long smlcCnt3 : 48; /* * [47:0]Event counter 3, count SMLC event from cnt_cfg */
#else
        unsigned long long smlcCnt3 : 48;     /* * [47:0]Event counter 3, count SMLC event from cnt_cfg */
        unsigned long long reserved : 16;     /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMLC_CNT3_U;

/* **
 * Union name :    SMLC_CNT_CFG0
 * @brief               Smart Memory Lock Cache Controller (SMLC) event counter configuration 0
 * Description:
 */
typedef union tagUnSmlcCntCfg0 {
    struct tagStSmlcCntCfg0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int cnt3MatchInstId : 6;     /* * [31:26]Counter 3 match instance ID */
        unsigned int cnt2MatchInstId : 6;     /* * [25:20]Counter 2 match instance ID */
        unsigned int cnt1MatchInstId : 6;     /* * [19:14]Counter 1 match instance ID */
        unsigned int cnt0MatchInstId : 6;     /* * [13:8]Counter 0 match instance ID */
        unsigned int cnt3InstMatchEnable : 1; /* * [7:7]Counter 3 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt3_match_inst_id
                                               */
        unsigned int cnt2InstMatchEnable : 1; /* * [6:6]Counter 2 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt2_match_inst_id
                                               */
        unsigned int cnt1InstMatchEnable : 1; /* * [5:5]Counter 1 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt1_match_inst_id
                                               */
        unsigned int cnt0InstMatchEnable : 1; /* * [4:4]Counter 0 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt0_match_inst_id
                                               */
        unsigned int cntEnable : 4;           /* * [3:0]Event counter enable for each counter */
#else
        unsigned int cntEnable : 4;           /* * [3:0]Event counter enable for each counter */
        unsigned int cnt0InstMatchEnable : 1; /* * [4:4]Counter 0 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt0_match_inst_id
                                               */
        unsigned int cnt1InstMatchEnable : 1; /* * [5:5]Counter 1 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt1_match_inst_id
                                               */
        unsigned int cnt2InstMatchEnable : 1; /* * [6:6]Counter 2 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt2_match_inst_id
                                               */
        unsigned int cnt3InstMatchEnable : 1; /* * [7:7]Counter 3 match instance ID enable,if enable, event counter only
                                               * monitor instance event that match with cnt3_match_inst_id
                                               */
        unsigned int cnt0MatchInstId : 6;     /* * [13:8]Counter 0 match instance ID */
        unsigned int cnt1MatchInstId : 6;     /* * [19:14]Counter 1 match instance ID */
        unsigned int cnt2MatchInstId : 6;     /* * [25:20]Counter 2 match instance ID */
        unsigned int cnt3MatchInstId : 6;     /* * [31:26]Counter 3 match instance ID */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_CNT_CFG0_U;

/* **
 * Union name :    SMLC_CNT_CFG1
 * @brief               Smart Memory Lock Cache Controller (SMLC) event counter configuration 1
 * Description:
 */
typedef union tagUnSmlcCntCfg1 {
    struct tagStSmlcCntCfg1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16;    /* * [31:16] */
        unsigned int cnt3EventSel : 4; /* * [15:12]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
        unsigned int cnt2EventSel : 4; /* * [11:8]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
        unsigned int cnt1EventSel : 4; /* * [7:4]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
        unsigned int cnt0EventSel : 4; /* * [3:0]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
#else
        unsigned int cnt0EventSel : 4; /* * [3:0]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
        unsigned int cnt1EventSel : 4; /* * [7:4]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
        unsigned int cnt2EventSel : 4; /* * [11:8]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
        unsigned int cnt3EventSel : 4; /* * [15:12]0:load hit;(all load hit,include load no          refill hit,load bpc
                                    hit, etc.)1:load miss;(all load hit,include load      no refill miss,load bpc miss,
                                    etc.)2 :load lock hit;(all load lock hit,     include load lock bpc hit, etc.)3:load
                                    lock miss;(all load lock miss,     include load lock bpc miss, etc.)4:load bpc;5:l
                                    oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include
                                    bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache
                                    invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */
        unsigned int reserved : 16;    /* * [31:16] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_CNT_CFG1_U;

/* **
 * Union name :    SMLC_CREDIT_CTP
 * @brief               Smart Memory Lock Cache Controller (SMLC)credit snapshot register.
 * Description:
 */
typedef union tagUnSmlcCreditCtp {
    struct tagStSmlcCreditCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 25;  /* * [31:7]reserved. */
        unsigned int vcCredit : 2;   /* * [6:5]bpc data credit value from Victim Cache.In SMF, the initial value is 0x1.
                                      */
        unsigned int smmcCredit : 5; /* * [4:0]credit value from SMMC.In SMF, the initial value is 0x4. In SML, the
                                      * initial value is 0x10.
                                      */
#else
        unsigned int smmcCredit : 5;   /* * [4:0]credit value from SMMC.In SMF, the initial value is 0x4. In SML, the
                                        * initial value is 0x10.
                                        */
        unsigned int vcCredit : 2;  /* * [6:5]bpc data credit value from Victim Cache.In SMF, the initial value is 0x1.
                                     */
        unsigned int reserved : 25; /* * [31:7]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_CREDIT_CTP_U;

/* **
 * Union name :    SMLC_FIFO_DEPTH_CTP
 * @brief               Smart Memory Lock Cache Controller (SMLC)fifo depth snapshot register.
 * Description:
 */
typedef union tagUnSmlcFifoDepthCtp {
    struct tagStSmlcFifoDepthCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 22;   /* * [31:10]reserved. */
        unsigned int reserved1 : 5;    /* * [9:5]reserved */
        unsigned int srfFifoDepth : 5; /* * [4:0]srf fifo real depth. */
#else
        unsigned int srfFifoDepth : 5;  /* * [4:0]srf fifo real depth. */
        unsigned int reserved1 : 5;     /* * [9:5]reserved */
        unsigned int reserved0 : 22;    /* * [31:10]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_FIFO_DEPTH_CTP_U;

/* **
 * Union name :    SMLC_ECC_ERR_CTP
 * @brief               Smart Memory Lock Cache Controller (SMLC)parity error snapshot register.
 * Description:
 */
typedef union tagUnSmlcEccErrCtp {
    struct tagStSmlcEccErrCtp {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int eccErrorInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error
                                    occur.Note: this field only capture the onformation of the last error.[31:16]
                                    reserved.[15:13] : information type. indicate which memory has ECC error.  0:fiar;
                                    1:pab;  2:stb;  3:cdb0;   4:cdb1;  5:bat;  other value:reserved.For fiar memory
                                    error:[12:8] reserved.[7:0] memory index;For pab memory error:[12:5] reserved.[4:0]
                                    memory index;For stb memory error:[12:8] reserved.[7:3] memory index;[2:0] index
                                    number o f error occured 16byte in a entry of data memory;For cdb0 memory
                                    error:[12:9] reserved.[8:3] memory index;[2:0] index number of error occured 16byte
                                    in a entry of data memory;For cdb1 memory error:[12:7] memory index;[6:0] index
                                    number of error occured byte in a entry of data memory;For bat memory error:[12:10]
                                    reserve d.[9:0] memory index; */
#else
        unsigned int eccErrorInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error
                                    occur.Note: this field only capture the onformation of the last error.[31:16]
                                    reserved.[15:13] : information type. indicate which memory has ECC error.  0:fiar;
                                    1:pab;  2:stb;  3:cdb0;   4:cdb1;  5:bat;  other value:reserved.For fiar memory
                                    error:[12:8] reserved.[7:0] memory index;For pab memory error:[12:5] reserved.[4:0]
                                    memory index;For stb memory error:[12:8] reserved.[7:3] memory index;[2:0] index
                                    number o f error occured 16byte in a entry of data memory;For cdb0 memory
                                    error:[12:9] reserved.[8:3] memory index;[2:0] index number of error occured 16byte
                                    in a entry of data memory;For cdb1 memory error:[12:7] memory index;[6:0] index
                                    number of error occured byte in a entry of data memory;For bat memory error:[12:10]
                                    reserve d.[9:0] memory index; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMLC_ECC_ERR_CTP_U;


/* **
 * Union name :    SMMC_F_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmmcFVersion {
    struct tagStSmmcFVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smmcFVersion : 32; /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_VERSION_U;

/* **
 * Union name :    SMMC_F_MC_CFG
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCfg {
    struct tagStSmmcFMcCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;     /* * [31:30] */
        unsigned int readSoRo : 2;     /* * [29:28]so_ro configure for read operation.so_ro: 2 bits, it specifies the
                                    ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict
                                    Ordering; 2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed
                                    Ordering and ID Based Ordering.
                                     */
        unsigned int writeSoRo : 2;    /* * [27:26]so_ro configure for write operation.so_ro: 2 bits, it specifies the
                                    ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict
                                    Ordering ;2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed
                                    Ordering and ID Based Ordering.
                                     */
        unsigned int memBankIdPst : 2; /* * [25:24]Bank id position in mem_index in memory mode, or stateless
                                    mode.0:bank_id = mem_index[3:2];1:bank_id = mem_index[4:3];2:bank_id =
                                    mem_index[5:4];3:bank_id = mem _index[6:5]; */
        unsigned int smmcQuStoreBpThd : 8; /* * [23:16]Qu store buffer backpressure threshold, in unit of 64Byte. If
                                            * available space in qu store buffer is less than this value,qu store API
                                            * will be blocked.
                                            */
        unsigned int smmcQuReturnFifoBp0ffThd : 6; /* * [15:10]Qu return fifo release backpressure threshold. If used
                                                    * space in qu return fifo is less than this value, the backpressure
                                                    * will be released.
                                                    */
        unsigned int smmcQuReturnFifoBponThd : 6;  /* * [9:4]Qu return fifo backpressure threshold. If used space in qu
                                               return fifo is no less than this value, the backpressure will be set, and
                                               qu load API will be blocked
                                               . */
        unsigned int smmcMcEccParityEnable : 1;    /* * [3:3]1'b1:enable ecc/parity check with memory read
                                                    * data;1'b0:disable ecc/parity check with memory read data;
                                                    */
        unsigned int smmcMcClaChkEnb : 1; /* * [2:2]1'b1:enable to check validation of CLA GPA.GPA[0] =1 means this GPA
                                           * is valid, GPA[0]=0 means this GPA is invalid.1'b0:disable to check
                                           * validation of CLA GPA.
                                           */
        unsigned int
            smmcFQuRxCtpEnb : 1; /* * [1:1]when this signal is enable, SMMC will capture first flit that received from
                              QU side.1'b1: enable;1'b0:
                              disable;注意：SMMC只抓该信号有效后从QU侧过来的第一个flit，抓住后保持不变；如果要重新抓新的fli
                              t，需要先把该信号拉低再拉高。 */
        unsigned int
            smmcFQuTxCtpEnb : 1; /* * [0:0]when this signal is enable, SMMC will capture first flit that sent to QU
                              side.1'b1: enable;1'b0:
                              disable;注意：SMMC只抓该信号有效后SMMC发给QU的第一个flit，抓住后保持不变；如果要重新抓新的flit，需要
                              先把该信号拉低再拉高。 */
#else
        unsigned int
            smmcFQuTxCtpEnb : 1; /* * [0:0]when this signal is enable, SMMC will capture first flit that sent to QU
                              side.1'b1: enable;1'b0:
                              disable;注意：SMMC只抓该信号有效后SMMC发给QU的第一个flit，抓住后保持不变；如果要重新抓新的flit，需要
                              先把该信号拉低再拉高。 */
        unsigned int
            smmcFQuRxCtpEnb : 1; /* * [1:1]when this signal is enable, SMMC will capture first flit that received from
                              QU side.1'b1: enable;1'b0:
                              disable;注意：SMMC只抓该信号有效后从QU侧过来的第一个flit，抓住后保持不变；如果要重新抓新的fli
                              t，需要先把该信号拉低再拉高。 */
        unsigned int smmcMcClaChkEnb : 1; /* * [2:2]1'b1:enable to check validation of CLA GPA.GPA[0] =1 means this GPA
                                           * is valid, GPA[0]=0 means this GPA is invalid.1'b0:disable to check
                                           * validation of CLA GPA.
                                           */
        unsigned int smmcMcEccParityEnable : 1;    /* * [3:3]1'b1:enable ecc/parity check with memory read
                                                    * data;1'b0:disable ecc/parity check with memory read data;
                                                    */
        unsigned int smmcQuReturnFifoBponThd : 6;  /* * [9:4]Qu return fifo backpressure threshold. If used space in qu
                                               return fifo is no less than this value, the backpressure will be set, and
                                               qu load API will be blocked
                                               . */
        unsigned int smmcQuReturnFifoBp0ffThd : 6; /* * [15:10]Qu return fifo release backpressure threshold. If used
                                                    * space in qu return fifo is less than this value, the backpressure
                                                    * will be released.
                                                    */
        unsigned int smmcQuStoreBpThd : 8; /* * [23:16]Qu store buffer backpressure threshold, in unit of 64Byte. If
                                            * available space in qu store buffer is less than this value,qu store API
                                            * will be blocked.
                                            */
        unsigned int memBankIdPst : 2;     /* * [25:24]Bank id position in mem_index in memory mode, or stateless
                                        mode.0:bank_id = mem_index[3:2];1:bank_id = mem_index[4:3];2:bank_id =
                                        mem_index[5:4];3:bank_id = mem _index[6:5]; */
        unsigned int writeSoRo : 2;     /* * [27:26]so_ro configure for write operation.so_ro: 2 bits, it specifies the
                                     ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict
                                     Ordering ;2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed
                                     Ordering and ID Based Ordering.
                                      */
        unsigned int readSoRo : 2;      /* * [29:28]so_ro configure for read operation.so_ro: 2 bits, it specifies the
                                     ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict
                                     Ordering; 2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed
                                     Ordering and ID Based Ordering.
                                      */
        unsigned int reserved : 2;      /* * [31:30] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CFG_U;

/* **
 * Union name :    SMMC_F_MC_CFG1
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCfg1 {
    struct tagStSmmcFMcCfg1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 2;   /* * [31:30] */
        unsigned int bankidSrc : 15; /* * [29:15]For cache mode, where bankid come from.0:bank id = hash
                                 value[4:3].1:bank id = smeg1_smlc_mem_index[4:3].Each bit is corresponding to each type
                                 configuration.Ba nkid_src[0] is corresponding to type1=p_cxt2.…Bankid_src[14] is
                                 corresponding to type15=others(GPA).
                                  */
        unsigned int cidSrc : 15;    /* * [14:0]For cache mode, where CID0/CID1 come from.0: CID0=hash value[22:14],
                                 CID1=hash value[13:5].1: CID0=CID1=smeg1_smlc_mem_index[13:5].Each bit is corresponding to
                                 each type configuration.cid_src[0] is corresponding to type1=p_cxt2.…cid_src[14] is
                                 corresponding to type15=others(GPA).
                                  */
#else
        unsigned int cidSrc : 15;       /* * [14:0]For cache mode, where CID0/CID1 come from.0: CID0=hash value[22:14],
                                    CID1=hash value[13:5].1: CID0=CID1=smeg1_smlc_mem_index[13:5].Each bit is corresponding to
                                    each type configuration.cid_src[0] is corresponding to type1=p_cxt2.…cid_src[14] is
                                    corresponding to type15=others(GPA).
                                     */
        unsigned int bankidSrc : 15;    /* * [29:15]For cache mode, where bankid come from.0:bank id = hash
                                    value[4:3].1:bank id = smeg1_smlc_mem_index[4:3].Each bit is corresponding to each type
                                    configuration.Ba nkid_src[0] is corresponding to type1=p_cxt2.…Bankid_src[14] is
                                    corresponding to type15=others(GPA).
                                     */
        unsigned int reserved : 2;      /* * [31:30] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CFG1_U;

/* **
* Union name :    SMMC_HASH_SEED0
* @brief               Hash function seed conifg register. This register used to change the original seed of hash
function.

* Description:
*/
typedef union tagUnSmmcHashSeed0 {
    struct tagStSmmcHashSeed0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int hashSeedCfg0 : 32; /* * [31:0] */
#else
        unsigned int hashSeedCfg0 : 32; /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_HASH_SEED0_U;

/* **
* Union name :    SMMC_HASH_SEED1
* @brief               Hash function seed conifg register. This register used to change the original seed of hash
function.

* Description:
*/
typedef union tagUnSmmcHashSeed1 {
    struct tagStSmmcHashSeed1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int hashSeedCfg1 : 32; /* * [31:0] */
#else
        unsigned int hashSeedCfg1 : 32; /* * [31:0] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_HASH_SEED1_U;

/* **
 * Union name :    SMMC_F_CFG
 * @brief               SMMF_F configuration register .
 * Description:
 */
typedef union tagUnSmmcFCfg {
    struct tagStSmmcFCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int memRet1nDiv2 : 1;   /* * [31:31]control of memory pin RET1N */
        unsigned int spRamTmodDiv2 : 7;  /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                          * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                          */
        unsigned int reserved : 2;       /* * [23:22]reserved */
        unsigned int smmcFBankVldId : 4; /* * [21:18]indicate which bank is
                                      valid,1'b1:valid;1'b0:invalid.Bit[0]:correspond to bank0;Bit[1]:correspond to
                                      bank1;Bit[2]:correspond to bank2;Bit[3]:correspond to bank3
                                      ; */
        unsigned int smmcFBankVldNum : 2; /* * [17:16]indicate how many banks are valid:2'b00: 4 banks are valid;2'b01:
                                       1 bank is valid;2'b10: 2 banks are valid;2'b11: reserved;Note: this signal only
                                       configure how many banks are valid, which bank is valid is cofigured by
                                       smmc_f_bank_vld_id. */
        unsigned int memRet1n : 1;        /* * [15:15]control of memory pin RET1N */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                     * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                     */
#else
        unsigned int tpRamTmod : 8;     /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT,
                                         * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0
                                         */
        unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256),
                                     * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                     */
        unsigned int memRet1n : 1;  /* * [15:15]control of memory pin RET1N */
        unsigned int smmcFBankVldNum : 2; /* * [17:16]indicate how many banks are valid:2'b00: 4 banks are valid;2'b01:
                                       1 bank is valid;2'b10: 2 banks are valid;2'b11: reserved;Note: this signal only
                                       configure how many banks are valid, which bank is valid is cofigured by
                                       smmc_f_bank_vld_id. */
        unsigned int smmcFBankVldId : 4;  /* * [21:18]indicate which bank is
                                       valid,1'b1:valid;1'b0:invalid.Bit[0]:correspond to bank0;Bit[1]:correspond to
                                       bank1;Bit[2]:correspond to bank2;Bit[3]:correspond to bank3
                                       ; */
        unsigned int reserved : 2;        /* * [23:22]reserved */
        unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                         * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                         */
        unsigned int memRet1nDiv2 : 1;  /* * [31:31]control of memory pin RET1N */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_CFG_U;

/* **
 * Union name :    SMMC_F_MC_INIT
 * @brief               SMMC_F main cache initialization
 * Description:
 */
typedef union tagUnSmmcFMcInit {
    struct tagStSmmcFMcInit {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 3;             /* * [31:29] */
        unsigned int smmcMcInitEndAddr : 14;   /* * [28:15]The end address in data memory to stop processing
                                                  initialization. */
        unsigned int smmcMcInitStartAddr : 14; /* * [14:1]The start address in data memory to begin processing
                                           initialization. The initialization only process in the region from the start
                                           address to the end address in four banks.Basically, only the memory mode
                                           region in data memory needs to initializing.
                                            */
        unsigned int smmcMcInit : 1; /* * [0:0]Write 1 to register will trigger one cycle pulse to start harware inital
                                      * invalidate all cache line entries(include tag memory and data memory) in main
                                      * cache.
                                      */
#else
        unsigned int smmcMcInit : 1; /* * [0:0]Write 1 to register will trigger one cycle pulse to start harware inital
                                      * invalidate all cache line entries(include tag memory and data memory) in main
                                      * cache.
                                      */
        unsigned int smmcMcInitStartAddr : 14;     /* * [14:1]The start address in data memory to begin processing
                                               initialization. The initialization only process in the region from the start
                                               address to the end address in four banks.Basically, only the memory mode
                                               region in data memory needs to initializing.
                                                */
        unsigned int smmcMcInitEndAddr : 14;       /* * [28:15]The end address in data memory to stop processing
                                                      initialization. */
        unsigned int reserved : 3;                 /* * [31:29] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_INIT_U;

/* **
 * Union name :    SMMC_F_MC_RF_TIMEOUT_INTERVAL
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcRfTimeoutInterval {
    struct tagStSmmcFMcRfTimeoutInterval {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcRefillTimeoutInterval : 32; /* * [31:0]the max interval for SMMC to refill data from host. if a
                                                    * refill operation interval exceed the configured interval, SMMC
                                                    * will report a timeout error to SW.
                                                    */
#else
        unsigned int mcRefillTimeoutInterval : 32; /* * [31:0]the max interval for SMMC to refill data from host. if a
                                                    * refill operation interval exceed the configured interval, SMMC
                                                    * will report a timeout error to SW.
                                                    */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_U;

/* **
 * Union name :    SMMC_F_INT_VECTOR
 * @brief               Statefull Smart Memory Memory Controller (SMMC_F) interrupt vector register
 * Description:
 */
typedef union tagUnSmmcFIntVector {
    struct tagStSmmcFIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29] */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int enable : 1;    /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                     * register0:interrupt disable1:interrupt enable
                                     */
        unsigned int reserved1 : 3; /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;       /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                        * register0:interrupt disable1:interrupt enable
                                        */
        unsigned int intIssue : 1;  /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need
                                     * to write 0 to clear.
                                     */
        unsigned int reserved0 : 3; /* * [31:29] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_INT_VECTOR_U;

/* **
 * Union name :    SMMC_F_INT
 * @brief               Smart Memory Memory Controller (SMMC) interrupt data register
 * Description:
 */
typedef union tagUnSmmcFInt {
    struct tagStSmmcFInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt.
                                         */
        unsigned int reserved : 9;      /* * [15:7]reserved */
        unsigned int intData : 7;       /* * [6:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 7;   /* * [6:0]interrupt masked field,it is the collection of the error bits from the
                                     * corresponding error registers on the sheet
                                     */
        unsigned int reserved : 9;  /* * [15:7]reserved */
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt.
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_INT_U;

/* **
 * Union name :    SMMC_F_INT_MASK
 * @brief               Statefull Smart Memory Memory Controller (SMMC_F) interrupt mask register.
 * Description:
 */
typedef union tagUnSmmcFIntMask {
    struct tagStSmmcFIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                    of CSR modules) asked for the interrupt.This register is used to mask any bits of
                                    the interru pt register. Software engineers can use this register to mask
                                    corresponding bits if they don not want these bits reporting to upper level.
                                     */
        unsigned int reserved : 9;      /* * [15:7] */
        unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 9;        /* * [15:7] */
        unsigned int programCsrId : 16;   /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group
                                      of CSR modules) asked for the interrupt.This register is used to mask any bits of
                                      the interru pt register. Software engineers can use this register to mask
                                      corresponding bits if they don not want these bits reporting to upper level.
                                       */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_INT_MASK_U;

/* **
 * Union name :    SMMC_F_MC_CACHE_ERR
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCacheErr {
    struct tagStSmmcFMcCacheErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcData32bEccMerr : 1; /* * [31:31]main cache bank3 data memory 2bit ECC multi error; */
        unsigned int mcData32bEccErr : 1;  /* * [30:30]main cache bank3 data memory 2bit ECC error; */
        unsigned int mcData31bEccMerr : 1; /* * [29:29]main cache bank3 data memory 1bit ECC multi error; */
        unsigned int mcData31bEccErr : 1;  /* * [28:28]main cache bank3 data memory 1bit ECC error; */
        unsigned int mcData22bEccMerr : 1; /* * [27:27]main cache bank2 data memory 2bit ECC multi error; */
        unsigned int mcData22bEccErr : 1;  /* * [26:26]main cache bank2 data memory 2bit ECC error; */
        unsigned int mcData21bEccMerr : 1; /* * [25:25]main cache bank2 data memory 1bit ECC multi error; */
        unsigned int mcData21bEccErr : 1;  /* * [24:24]main cache bank2 data memory 1bit ECC error; */
        unsigned int mcData12bEccMerr : 1; /* * [23:23]main cache bank1 data memory 2bit ECC multi error; */
        unsigned int mcData12bEccErr : 1;  /* * [22:22]main cache bank1 data memory 2bit ECC error; */
        unsigned int mcData11bEccMerr : 1; /* * [21:21]main cache bank1 data memory 1bit ECC multi error; */
        unsigned int mcData11bEccErr : 1;  /* * [20:20]main cache bank1 data memory 1bit ECC error; */
        unsigned int mcData02bEccMerr : 1; /* * [19:19]main cache bank0 data memory 2bit ECC multi error; */
        unsigned int mcData02bEccErr : 1;  /* * [18:18]main cache bank0 data memory 2bit ECC error; */
        unsigned int mcData01bEccMerr : 1; /* * [17:17]main cache bank0 data memory 1bit ECC multi error; */
        unsigned int mcData01bEccErr : 1;  /* * [16:16]main cache bank0 data memory 1bit ECC error; */
        unsigned int mcTag32bEccMerr : 1;  /* * [15:15]main cache bank3 tag memory 2bit ECC multi error; */
        unsigned int mcTag32bEccErr : 1;   /* * [14:14]main cache bank3 tag memory 2bit ECC error; */
        unsigned int mcTag31bEccMerr : 1;  /* * [13:13]main cache bank3 tag memory 1bit ECC multi error; */
        unsigned int mcTag31bEccErr : 1;   /* * [12:12]main cache bank3 tag memory 1bit ECC error; */
        unsigned int mcTag22bEccMerr : 1;  /* * [11:11]main cache bank2 tag memory 2bit ECC multi error; */
        unsigned int mcTag22bEccErr : 1;   /* * [10:10]main cache bank2 tag memory 2bit ECC error; */
        unsigned int mcTag21bEccMerr : 1;  /* * [9:9]main cache bank2 tag memory 1bit ECC multi error; */
        unsigned int mcTag21bEccErr : 1;   /* * [8:8]main cache bank2 tag memory 1bit ECC error; */
        unsigned int mcTag12bEccMerr : 1;  /* * [7:7]main cache bank1 tag memory 2bit ECC multi error; */
        unsigned int mcTag12bEccErr : 1;   /* * [6:6]main cache bank1 tag memory 2bit ECC error; */
        unsigned int mcTag11bEccMerr : 1;  /* * [5:5]main cache bank1 tag memory 1bit ECC multi error; */
        unsigned int mcTag11bEccErr : 1;   /* * [4:4]main cache bank1 tag memory 1bit ECC error; */
        unsigned int mcTag02bEccMerr : 1;  /* * [3:3]main cache bank0 tag memory 2bit ECC multi error; */
        unsigned int mcTag02bEccErr : 1;   /* * [2:2]main cache bank0 tag memory 2bit ECC error; */
        unsigned int mcTag01bEccMerr : 1;  /* * [1:1]main cache bank0 tag memory 1bit ECC multi error; */
        unsigned int mcTag01bEccErr : 1;   /* * [0:0]main cache bank0 tag memory 1bit ECC error; */
#else
        unsigned int mcTag01bEccErr : 1;  /* * [0:0]main cache bank0 tag memory 1bit ECC error; */
        unsigned int mcTag01bEccMerr : 1; /* * [1:1]main cache bank0 tag memory 1bit ECC multi error; */
        unsigned int mcTag02bEccErr : 1;  /* * [2:2]main cache bank0 tag memory 2bit ECC error; */
        unsigned int mcTag02bEccMerr : 1; /* * [3:3]main cache bank0 tag memory 2bit ECC multi error; */
        unsigned int mcTag11bEccErr : 1;  /* * [4:4]main cache bank1 tag memory 1bit ECC error; */
        unsigned int mcTag11bEccMerr : 1; /* * [5:5]main cache bank1 tag memory 1bit ECC multi error; */
        unsigned int mcTag12bEccErr : 1;  /* * [6:6]main cache bank1 tag memory 2bit ECC error; */
        unsigned int mcTag12bEccMerr : 1; /* * [7:7]main cache bank1 tag memory 2bit ECC multi error; */
        unsigned int mcTag21bEccErr : 1;  /* * [8:8]main cache bank2 tag memory 1bit ECC error; */
        unsigned int mcTag21bEccMerr : 1; /* * [9:9]main cache bank2 tag memory 1bit ECC multi error; */
        unsigned int mcTag22bEccErr : 1;  /* * [10:10]main cache bank2 tag memory 2bit ECC error; */
        unsigned int mcTag22bEccMerr : 1; /* * [11:11]main cache bank2 tag memory 2bit ECC multi error; */
        unsigned int mcTag31bEccErr : 1;  /* * [12:12]main cache bank3 tag memory 1bit ECC error; */
        unsigned int mcTag31bEccMerr : 1; /* * [13:13]main cache bank3 tag memory 1bit ECC multi error; */
        unsigned int mcTag32bEccErr : 1;  /* * [14:14]main cache bank3 tag memory 2bit ECC error; */
        unsigned int mcTag32bEccMerr : 1; /* * [15:15]main cache bank3 tag memory 2bit ECC multi error; */
        unsigned int mcData01bEccErr : 1; /* * [16:16]main cache bank0 data memory 1bit ECC error; */
        unsigned int mcData01bEccMerr : 1;    /* * [17:17]main cache bank0 data memory 1bit ECC multi error; */
        unsigned int mcData02bEccErr : 1;     /* * [18:18]main cache bank0 data memory 2bit ECC error; */
        unsigned int mcData02bEccMerr : 1;    /* * [19:19]main cache bank0 data memory 2bit ECC multi error; */
        unsigned int mcData11bEccErr : 1;     /* * [20:20]main cache bank1 data memory 1bit ECC error; */
        unsigned int mcData11bEccMerr : 1;    /* * [21:21]main cache bank1 data memory 1bit ECC multi error; */
        unsigned int mcData12bEccErr : 1;     /* * [22:22]main cache bank1 data memory 2bit ECC error; */
        unsigned int mcData12bEccMerr : 1;    /* * [23:23]main cache bank1 data memory 2bit ECC multi error; */
        unsigned int mcData21bEccErr : 1;     /* * [24:24]main cache bank2 data memory 1bit ECC error; */
        unsigned int mcData21bEccMerr : 1;    /* * [25:25]main cache bank2 data memory 1bit ECC multi error; */
        unsigned int mcData22bEccErr : 1;     /* * [26:26]main cache bank2 data memory 2bit ECC error; */
        unsigned int mcData22bEccMerr : 1;    /* * [27:27]main cache bank2 data memory 2bit ECC multi error; */
        unsigned int mcData31bEccErr : 1;     /* * [28:28]main cache bank3 data memory 1bit ECC error; */
        unsigned int mcData31bEccMerr : 1;    /* * [29:29]main cache bank3 data memory 1bit ECC multi error; */
        unsigned int mcData32bEccErr : 1;     /* * [30:30]main cache bank3 data memory 2bit ECC error; */
        unsigned int mcData32bEccMerr : 1;    /* * [31:31]main cache bank3 data memory 2bit ECC multi error; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CACHE_ERR_U;

/* **
 * Union name :    SMMC_F_MC_CACHE_MASK
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCacheMask {
    struct tagStSmmcFMcCacheMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16;           /* * [31:16]reserved. */
        unsigned int mcData32bEccErrMask : 1; /* * [15:15] */
        unsigned int mcData31bEccErrMask : 1; /* * [14:14] */
        unsigned int mcData22bEccErrMask : 1; /* * [13:13] */
        unsigned int mcData21bEccErrMask : 1; /* * [12:12] */
        unsigned int mcData12bEccErrMask : 1; /* * [11:11] */
        unsigned int mcData11bEccErrMask : 1; /* * [10:10] */
        unsigned int mcData02bEccErrMask : 1; /* * [9:9] */
        unsigned int mcData01bEccErrMask : 1; /* * [8:8] */
        unsigned int mcTag32bEccErrMask : 1;  /* * [7:7] */
        unsigned int mcTag31bEccErrMask : 1;  /* * [6:6] */
        unsigned int mcTag22bEccErrMask : 1;  /* * [5:5] */
        unsigned int mcTag21bEccErrMask : 1;  /* * [4:4] */
        unsigned int mcTag12bEccErrMask : 1;  /* * [3:3] */
        unsigned int mcTag11bEccErrMask : 1;  /* * [2:2] */
        unsigned int mcTag02bEccErrMask : 1;  /* * [1:1] */
        unsigned int mcTag01bEccErrMask : 1;  /* * [0:0] */
#else
        unsigned int mcTag01bEccErrMask : 1;  /* * [0:0] */
        unsigned int mcTag02bEccErrMask : 1;  /* * [1:1] */
        unsigned int mcTag11bEccErrMask : 1;  /* * [2:2] */
        unsigned int mcTag12bEccErrMask : 1;  /* * [3:3] */
        unsigned int mcTag21bEccErrMask : 1;  /* * [4:4] */
        unsigned int mcTag22bEccErrMask : 1;  /* * [5:5] */
        unsigned int mcTag31bEccErrMask : 1;  /* * [6:6] */
        unsigned int mcTag32bEccErrMask : 1;  /* * [7:7] */
        unsigned int mcData01bEccErrMask : 1; /* * [8:8] */
        unsigned int mcData02bEccErrMask : 1; /* * [9:9] */
        unsigned int mcData11bEccErrMask : 1; /* * [10:10] */
        unsigned int mcData12bEccErrMask : 1; /* * [11:11] */
        unsigned int mcData21bEccErrMask : 1; /* * [12:12] */
        unsigned int mcData22bEccErrMask : 1; /* * [13:13] */
        unsigned int mcData31bEccErrMask : 1; /* * [14:14] */
        unsigned int mcData32bEccErrMask : 1; /* * [15:15] */
        unsigned int reserved : 16;           /* * [31:16]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CACHE_MASK_U;

/* **
 * Union name :    SMMC_F_MC_CACHE_ERR_INFO
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCacheErrInfo {
    struct tagStSmmcFMcCacheErrInfo {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int
            mcCacheErrInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error
                             occur(corresponding to "SMMC_F_MC_CACHE_ERR").Note: this field only capture the onformation
                             of the last error.[31]: information valid flag. once there is ECC error occurs to any main
                             cache memory(tag memory or data memory),the bit will set valid.[30:28]: information type.
                             indicate which memory has ECC error.  3'b000: tag memory in bank0;  3'b001: tag memory in
                             bank1;  3'b010: tag memory in bank2;  3'b011: tag m emory in bank3;  3'b100: data memory in
                             bank0;  3'b101: data memory in bank1;  3'b110: data memory in bank2;  3'b111: data memory
                             in bank3;For main cache tag me mory error:[27:14] reserved.[13] error type:     1'b0: 1-bit
                             ECC error.     1'b1: 2-bit ECC error.[12] tag memory way number in a bank(corresponding to
                             CID0 or CID1);[11:2] memory address;[1:0] indicate which 16Byte has ECC error;For main
                             cache data memory error:[27:18] reserved.[17] error type:     1'b0: 1-bit ECC err or. 1'b1:
                             2-bit ECC error.[16:2] memory address;[1:0] indicate which 16Byte has ECC error;
                              */
#else
        unsigned int
            mcCacheErrInfo : 32;           /* * [31:0]This field will capture the information when main cache ECC error
                                       occur(corresponding to "SMMC_F_MC_CACHE_ERR").Note: this field only capture the onformation
                                       of the last error.[31]: information valid flag. once there is ECC error occurs to any main
                                       cache memory(tag memory or data memory),the bit will set valid.[30:28]: information type.
                                       indicate which memory has ECC error.  3'b000: tag memory in bank0;  3'b001: tag memory in
                                       bank1;  3'b010: tag memory in bank2;  3'b011: tag m emory in bank3;  3'b100: data memory in
                                       bank0;  3'b101: data memory in bank1;  3'b110: data memory in bank2;  3'b111: data memory
                                       in bank3;For main cache tag me mory error:[27:14] reserved.[13] error type:     1'b0: 1-bit
                                       ECC error.     1'b1: 2-bit ECC error.[12] tag memory way number in a bank(corresponding to
                                       CID0 or CID1);[11:2] memory address;[1:0] indicate which 16Byte has ECC error;For main
                                       cache data memory error:[27:18] reserved.[17] error type:     1'b0: 1-bit ECC err or. 1'b1:
                                       2-bit ECC error.[16:2] memory address;[1:0] indicate which 16Byte has ECC error;
                                        */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CACHE_ERR_INFO_U;

/* **
 * Union name :    SMMC_F_BUFFER_ERR
 * @brief
 * Description:
 */
typedef union tagUnSmmcFBufferErr {
    struct tagStSmmcFBufferErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int fifoOvfMerr : 1;         /* * [31:31]fifo overflow multi error in main cache or victim cache. */
        unsigned int fifoOvfErr : 1;          /* * [30:30]fifo overflow error in main cache or victim cache. */
        unsigned int directwqeMerr : 1;       /* * [29:29]direct WQE e0/e1 multi error. */
        unsigned int directwqeErr : 1;        /* * [28:28]direct WQE e0/e1 error. */
        unsigned int vcSmxtfBuf2bEccMerr : 1; /* * [27:27]victim cache smxt interface output fifo 2bit ECC multi error.
                                               */
        unsigned int vcSmxtfBuf2bEccErr : 1;  /* * [26:26]victim cache smxt interface output fifo 2bit ECC error. */
        unsigned int vcSmxtfBuf1bEccMerr : 1; /* * [25:25]victim cache smxt interface output fifo 1bit ECC multi error.
                                               */
        unsigned int vcSmxtfBuf1bEccErr : 1;  /* * [24:24]victim cache smxt interface output fifo 1bit ECC error. */
        unsigned int mcRfbuf2bEccMerr : 1;    /* * [23:23]main cache refill data buffer 2bit ECC multi error. */
        unsigned int mcRfbuf2bEccErr : 1;     /* * [22:22]main cache refill data buffer 2bit ECC error. */
        unsigned int mcRfbuf1bEccMerr : 1;    /* * [21:21]main cache refill data buffer 1bit ECC multi error. */
        unsigned int mcRfbuf1bEccErr : 1;     /* * [20:20]main cache refill data buffer 1bit ECC error. */
        unsigned int mcQuDatafifo2bEccMerr : 1; /* * [19:19]main cache qu data fifo 2bit ECC multi error. */
        unsigned int mcQuDatafifo2bEccErr : 1;  /* * [18:18]main cache qu data fifo 2bit ECC error. */
        unsigned int mcQuDatafifo1bEccMerr : 1; /* * [17:17]main cache qu data fifo 1bit ECC multi error. */
        unsigned int mcQuDatafifo1bEccErr : 1;  /* * [16:16]main cache qu data fifo 1bit ECC error. */
        unsigned int mcQuLrn2bEccMerr : 1;      /* * [15:15]main cache qu lrn data buffer 2bit ECC multi error. */
        unsigned int mcQuLrn2bEccErr : 1;       /* * [14:14]main cache qu lrn data buffer 2bit ECC error. */
        unsigned int mcQuLrn1bEccMerr : 1;      /* * [13:13]main cache qu lrn data buffer 1bit ECC multi error. */
        unsigned int mcQuLrn1bEccErr : 1;       /* * [12:12]main cache qu lrn data buffer 1bit ECC error. */
        unsigned int mcQuStbuf2bEccMerr : 1;    /* * [11:11]main cache qu store data buffer 2bit ECC multi error. */
        unsigned int mcQuStbuf2bEccErr : 1;     /* * [10:10]main cache qu store data buffer 2bit ECC error. */
        unsigned int mcQuStbuf1bEccMerr : 1;    /* * [9:9]main cache qu store data buffer 1bit ECC multi error. */
        unsigned int mcQuStbuf1bEccErr : 1;     /* * [8:8]main cache qu store data buffer 1bit ECC error. */
        unsigned int mcEngStbuf2bEccMerr : 1;   /* * [7:7]main cache engine store data buffer 2bit ECC multi error. */
        unsigned int mcEngStbuf2bEccErr : 1;    /* * [6:6]main cache engine store data buffer 2bit ECC error. */
        unsigned int mcEngStbuf1bEccMerr : 1;   /* * [5:5]main cache engine store data buffer 1bit ECC multi error. */
        unsigned int mcEngStbuf1bEccErr : 1;    /* * [4:4]main cache engine store data buffer 1bit ECC error. */
        unsigned int mcQuVfa2bEccMerr : 1;      /* * [3:3]main cache VFA table 2bit ECC multi error. */
        unsigned int mcQuVfa2bEccErr : 1;       /* * [2:2]main cache VFA table 2bit ECC error. */
        unsigned int mcQuVfa1bEccMerr : 1;      /* * [1:1]main cache VFA table 1bit ECC multi error. */
        unsigned int mcQuVfa1bEccErr : 1;       /* * [0:0]main cache VFA table 1bit ECC error. */
#else
        unsigned int mcQuVfa1bEccErr : 1;  /* * [0:0]main cache VFA table 1bit ECC error. */
        unsigned int mcQuVfa1bEccMerr : 1; /* * [1:1]main cache VFA table 1bit ECC multi error. */
        unsigned int mcQuVfa2bEccErr : 1;  /* * [2:2]main cache VFA table 2bit ECC error. */
        unsigned int mcQuVfa2bEccMerr : 1; /* * [3:3]main cache VFA table 2bit ECC multi error. */
        unsigned int mcEngStbuf1bEccErr : 1;    /* * [4:4]main cache engine store data buffer 1bit ECC error. */
        unsigned int mcEngStbuf1bEccMerr : 1;   /* * [5:5]main cache engine store data buffer 1bit ECC multi error. */
        unsigned int mcEngStbuf2bEccErr : 1;    /* * [6:6]main cache engine store data buffer 2bit ECC error. */
        unsigned int mcEngStbuf2bEccMerr : 1;   /* * [7:7]main cache engine store data buffer 2bit ECC multi error. */
        unsigned int mcQuStbuf1bEccErr : 1;     /* * [8:8]main cache qu store data buffer 1bit ECC error. */
        unsigned int mcQuStbuf1bEccMerr : 1;    /* * [9:9]main cache qu store data buffer 1bit ECC multi error. */
        unsigned int mcQuStbuf2bEccErr : 1;     /* * [10:10]main cache qu store data buffer 2bit ECC error. */
        unsigned int mcQuStbuf2bEccMerr : 1;    /* * [11:11]main cache qu store data buffer 2bit ECC multi error. */
        unsigned int mcQuLrn1bEccErr : 1;       /* * [12:12]main cache qu lrn data buffer 1bit ECC error. */
        unsigned int mcQuLrn1bEccMerr : 1;      /* * [13:13]main cache qu lrn data buffer 1bit ECC multi error. */
        unsigned int mcQuLrn2bEccErr : 1;       /* * [14:14]main cache qu lrn data buffer 2bit ECC error. */
        unsigned int mcQuLrn2bEccMerr : 1;      /* * [15:15]main cache qu lrn data buffer 2bit ECC multi error. */
        unsigned int mcQuDatafifo1bEccErr : 1;  /* * [16:16]main cache qu data fifo 1bit ECC error. */
        unsigned int mcQuDatafifo1bEccMerr : 1; /* * [17:17]main cache qu data fifo 1bit ECC multi error. */
        unsigned int mcQuDatafifo2bEccErr : 1;  /* * [18:18]main cache qu data fifo 2bit ECC error. */
        unsigned int mcQuDatafifo2bEccMerr : 1; /* * [19:19]main cache qu data fifo 2bit ECC multi error. */
        unsigned int mcRfbuf1bEccErr : 1;       /* * [20:20]main cache refill data buffer 1bit ECC error. */
        unsigned int mcRfbuf1bEccMerr : 1;      /* * [21:21]main cache refill data buffer 1bit ECC multi error. */
        unsigned int mcRfbuf2bEccErr : 1;       /* * [22:22]main cache refill data buffer 2bit ECC error. */
        unsigned int mcRfbuf2bEccMerr : 1;      /* * [23:23]main cache refill data buffer 2bit ECC multi error. */
        unsigned int vcSmxtfBuf1bEccErr : 1;    /* * [24:24]victim cache smxt interface output fifo 1bit ECC error. */
        unsigned int vcSmxtfBuf1bEccMerr : 1; /* * [25:25]victim cache smxt interface output fifo 1bit ECC multi error.
                                               */
        unsigned int vcSmxtfBuf2bEccErr : 1;  /* * [26:26]victim cache smxt interface output fifo 2bit ECC error. */
        unsigned int vcSmxtfBuf2bEccMerr : 1; /* * [27:27]victim cache smxt interface output fifo 2bit ECC multi error.
                                               */
        unsigned int directwqeErr : 1;        /* * [28:28]direct WQE e0/e1 error. */
        unsigned int directwqeMerr : 1;       /* * [29:29]direct WQE e0/e1 multi error. */
        unsigned int fifoOvfErr : 1;          /* * [30:30]fifo overflow error in main cache or victim cache. */
        unsigned int fifoOvfMerr : 1;         /* * [31:31]fifo overflow multi error in main cache or victim cache. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_BUFFER_ERR_U;

/* **
 * Union name :    SMMC_F_BUFFER_MASK
 * @brief
 * Description:
 */
typedef union tagUnSmmcFBufferMask {
    struct tagStSmmcFBufferMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16;                /* * [31:16]reserved. */
        unsigned int fifoOvfErrMask : 1;           /* * [15:15] */
        unsigned int directwqeErrMask : 1;         /* * [14:14] */
        unsigned int vcSmxtfBuf2bEccErrMask : 1;   /* * [13:13] */
        unsigned int vcSmxtfBuf1bEccErrMask : 1;   /* * [12:12] */
        unsigned int mcRfbuf2bEccErrMask : 1;      /* * [11:11] */
        unsigned int mcRfbuf1bEccErrMask : 1;      /* * [10:10] */
        unsigned int mcQuDatafifo2bEccErrMask : 1; /* * [9:9] */
        unsigned int mcQuDatafifo1bEccErrMask : 1; /* * [8:8] */
        unsigned int mcQuLrn2bEccErrMask : 1;      /* * [7:7] */
        unsigned int mcQuLrn1bEccErrMask : 1;      /* * [6:6] */
        unsigned int mcQuStbuf2bEccErrMask : 1;    /* * [5:5] */
        unsigned int mcQuStbuf1bEccErrMask : 1;    /* * [4:4] */
        unsigned int mcEngStbuf2bEccErrMask : 1;   /* * [3:3] */
        unsigned int mcEngStbuf1bEccErrMask : 1;   /* * [2:2] */
        unsigned int mcQuVfa2bEccErrMask : 1;      /* * [1:1] */
        unsigned int mcQuVfa1bEccErrMask : 1;      /* * [0:0] */
#else
        unsigned int mcQuVfa1bEccErrMask : 1; /* * [0:0] */
        unsigned int mcQuVfa2bEccErrMask : 1; /* * [1:1] */
        unsigned int mcEngStbuf1bEccErrMask : 1;   /* * [2:2] */
        unsigned int mcEngStbuf2bEccErrMask : 1;   /* * [3:3] */
        unsigned int mcQuStbuf1bEccErrMask : 1;    /* * [4:4] */
        unsigned int mcQuStbuf2bEccErrMask : 1;    /* * [5:5] */
        unsigned int mcQuLrn1bEccErrMask : 1;      /* * [6:6] */
        unsigned int mcQuLrn2bEccErrMask : 1;      /* * [7:7] */
        unsigned int mcQuDatafifo1bEccErrMask : 1; /* * [8:8] */
        unsigned int mcQuDatafifo2bEccErrMask : 1; /* * [9:9] */
        unsigned int mcRfbuf1bEccErrMask : 1;      /* * [10:10] */
        unsigned int mcRfbuf2bEccErrMask : 1;      /* * [11:11] */
        unsigned int vcSmxtfBuf1bEccErrMask : 1;   /* * [12:12] */
        unsigned int vcSmxtfBuf2bEccErrMask : 1;   /* * [13:13] */
        unsigned int directwqeErrMask : 1;         /* * [14:14] */
        unsigned int fifoOvfErrMask : 1;           /* * [15:15] */
        unsigned int reserved : 16;                /* * [31:16]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_BUFFER_MASK_U;

/* **
 * Union name :    SMMC_F_BUFFER_ERR_INFO
 * @brief
 * Description:
 */
typedef union tagUnSmmcFBufferErrInfo {
    struct tagStSmmcFBufferErrInfo {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int
            mcBufferErrInfo : 32; /* * [31:0]This field will capture the information when other buffer memory ECC error
                              occur(corresponding to "SMMC_F_BUFFER_ERR").Note: this field only capture the informa tion
                              of the last error.[31]: information valid flag. once there is ECC error occurs to any
                              buffer memory,this bit will set valid.[30:28]: information type. indi cate which buffer
                              memory has ECC error.  3'b000: VFA table;  3'b001: engine store data buffer;  3'b010: qu
                              store data buffer;  3'b011: qu lrn data buffer;  3'b1 00: qu data fifo;  3'b101: refill
                              data buffer;  3'b110: vc smxtf buffer;  3'b111: fifo overflow;For VFA table:[27:11]
                              reserved.[10] error type:     1'b0: 1-bit ECC error.     1'b1: 2-bit ECC error.[9:0]
                              memory address. For engine store data buffer:[27:11] reserved.[10] error type:     1'b0:
                              1-bit ECC error.     1'b1: 2 -bit ECC error.[9] buffer number:    1'b0: buffer0;    1'b1:
                              buffer1;[8:3] memory access index (SMMC outstanding tag).[2:0] The error 16B position in
                              64B.  For qu store data buffer:[27:9] reserved.[8] error type:     1'b0: 1-bit ECC error.
                              1'b1: 2-bit ECC error.[7:0] memory access address.For qu lrn data buffer:[27 :7]
                              reserved.[6] error type:     1'b0: 1-bit ECC error.     1'b1: 2-bit ECC error.[5:0] memory
                              access address.For qu data fifo:[27:6] reserved.[5] error type: 1'b0: 1-bit ECC error.
                              1'b1: 2-bit ECC error.[4:0] memory access address.For refill data buffer:[27:9]
                              reserved.[8] error type:     1'b0: 1-bit ECC error .     1'b1: 2-bit ECC error.[7:0]
                              memory access address. For VC smxtf buffer:[27:6] reserved[5] error type:     1'b0: 1-bit
                              ECC error.     1'b1: 2-bit ECC error
                              .[4:0] memory access address.For fifo overflow, indicate which fifo is overflow:[15]:qu
                              command bimap error;[14]:qu command csize error;[13]:qu command tag type error;[12]:victim
                              cache3 write back fifo overflow;[11]:victim cache2 write back fifo overflow;[10]:victim
                              cache1 write back fifo overflow;[9]:victim cache0 wri te back fifo overflow;[8]:bank3 rcb
                              refill response fifo overflow;[7]:bank2 rcb refill response fifo overflow;[6]:bank1 rcb
                              refill response fifo overflow;[5]:ba nk0 rcb refill response fifo overflow;[4]:smxr refill
                              response fifo overflow;[3]:qu store ack fifo overflow;[2]:qu lrn fifo overflow;[1]:qu data
                              fifo overflow;[ 0]:qu command fifo overflow; */
#else
        unsigned int
            mcBufferErrInfo : 32;  /* * [31:0]This field will capture the information when other buffer memory ECC error
                               occur(corresponding to "SMMC_F_BUFFER_ERR").Note: this field only capture the informa tion
                               of the last error.[31]: information valid flag. once there is ECC error occurs to any
                               buffer memory,this bit will set valid.[30:28]: information type. indi cate which buffer
                               memory has ECC error.  3'b000: VFA table;  3'b001: engine store data buffer;  3'b010: qu
                               store data buffer;  3'b011: qu lrn data buffer;  3'b1 00: qu data fifo;  3'b101: refill
                               data buffer;  3'b110: vc smxtf buffer;  3'b111: fifo overflow;For VFA table:[27:11]
                               reserved.[10] error type:     1'b0: 1-bit ECC error.     1'b1: 2-bit ECC error.[9:0]
                               memory address. For engine store data buffer:[27:11] reserved.[10] error type:     1'b0:
                               1-bit ECC error.     1'b1: 2 -bit ECC error.[9] buffer number:    1'b0: buffer0;    1'b1:
                               buffer1;[8:3] memory access index (SMMC outstanding tag).[2:0] The error 16B position in
                               64B.  For qu store data buffer:[27:9] reserved.[8] error type:     1'b0: 1-bit ECC error.
                               1'b1: 2-bit ECC error.[7:0] memory access address.For qu lrn data buffer:[27 :7]
                               reserved.[6] error type:     1'b0: 1-bit ECC error.     1'b1: 2-bit ECC error.[5:0] memory
                               access address.For qu data fifo:[27:6] reserved.[5] error type: 1'b0: 1-bit ECC error.
                               1'b1: 2-bit ECC error.[4:0] memory access address.For refill data buffer:[27:9]
                               reserved.[8] error type:     1'b0: 1-bit ECC error .     1'b1: 2-bit ECC error.[7:0]
                               memory access address. For VC smxtf buffer:[27:6] reserved[5] error type:     1'b0: 1-bit
                               ECC error.     1'b1: 2-bit ECC error
                               .[4:0] memory access address.For fifo overflow, indicate which fifo is overflow:[15]:qu
                               command bimap error;[14]:qu command csize error;[13]:qu command tag type error;[12]:victim
                               cache3 write back fifo overflow;[11]:victim cache2 write back fifo overflow;[10]:victim
                               cache1 write back fifo overflow;[9]:victim cache0 wri te back fifo overflow;[8]:bank3 rcb
                               refill response fifo overflow;[7]:bank2 rcb refill response fifo overflow;[6]:bank1 rcb
                               refill response fifo overflow;[5]:ba nk0 rcb refill response fifo overflow;[4]:smxr refill
                               response fifo overflow;[3]:qu store ack fifo overflow;[2]:qu lrn fifo overflow;[1]:qu data
                               fifo overflow;[ 0]:qu command fifo overflow; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_BUFFER_ERR_INFO_U;

/* **
 * Union name :    SMMC_F_MC_RF_RTN_ERR
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcRfRtnErr {
    struct tagStSmmcFMcRfRtnErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2][31:2]:reserved;Note：the error information is captured in a proprietary
                               register, which could be read via indirect CSR access(via indirect memory/register group
                               "4'd14: qu interface capture data flit AND smf refill error captured information").
                               */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int errorBit : 1;      /* * [0:0]0:no error found1:error found */
#else
        unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int sticky : 30;  /* * [31:2][31:2]:reserved;Note：the error information is captured in a proprietary
                                register, which could be read via indirect CSR access(via indirect memory/register group
                                "4'd14: qu interface capture data flit AND smf refill error captured information").
                                */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_RF_RTN_ERR_U;

/* **
 * Union name :    SMMC_F_MC_RF_TIMEOUT_ERR
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcRfTimeoutErr {
    struct tagStSmmcFMcRfTimeoutErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;       /* * [31:2][31:2]:reserved; */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int errorBit : 1;      /* * [0:0]0:no error found1:error found */
#else
        unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */
        unsigned int multiErrorBit : 1;    /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int sticky : 30;          /* * [31:2][31:2]:reserved; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_RF_TIMEOUT_ERR_U;

/* **
 * Union name :    SMMC_F_MC_MULTI_HIT_ERR
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcMultiHitErr {
    struct tagStSmmcFMcMultiHitErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30;       /* * [31:2][31:30]: reserved;[29]: multiple hit both in main cache and victim
                                    cache;[28]: multiple hit in main cache;[27:24]: tag type;[23:22]: BANK-ID;[21:12]:
                                    CID1;[11:2
                                    ]: CID0; */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int errorBit : 1;      /* * [0:0]0:no error found1:error found */
#else
        unsigned int errorBit : 1;         /* * [0:0]0:no error found1:error found */
        unsigned int multiErrorBit : 1;    /* * [1:1]0:not more than 1 error found1:more than 1 errors found */
        unsigned int sticky : 30;          /* * [31:2][31:30]: reserved;[29]: multiple hit both in main cache and victim
                                       cache;[28]: multiple hit in main cache;[27:24]: tag type;[23:22]: BANK-ID;[21:12]:
                                       CID1;[11:2
                                       ]: CID0; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_MULTI_HIT_ERR_U;

/* **
 * Union name :    SMMC_F_VC_CACHE_ERR
 * @brief
 * Description:
 */
typedef union tagUnSmmcFVcCacheErr {
    struct tagStSmmcFVcCacheErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int vcData32bEccMerr : 1; /* * [31:31]victim cache bank3 data memory 2bit ECC multi error; */
        unsigned int vcData32bEccErr : 1;  /* * [30:30]victim cache bank3 data memory 2bit ECC error; */
        unsigned int vcData31bEccMerr : 1; /* * [29:29]victim cache bank3 data memory 1bit ECC multi error; */
        unsigned int vcData31bEccErr : 1;  /* * [28:28]victim cache bank3 data memory 1bit ECC error; */
        unsigned int vcData22bEccMerr : 1; /* * [27:27]victim cache bank2 data memory 2bit ECC multi error; */
        unsigned int vcData22bEccErr : 1;  /* * [26:26]victim cache bank2 data memory 2bit ECC error; */
        unsigned int vcData21bEccMerr : 1; /* * [25:25]victim cache bank2 data memory 1bit ECC multi error; */
        unsigned int vcData21bEccErr : 1;  /* * [24:24]victim cache bank2 data memory 1bit ECC error; */
        unsigned int vcData12bEccMerr : 1; /* * [23:23]victim cache bank1 data memory 2bit ECC multi error; */
        unsigned int vcData12bEccErr : 1;  /* * [22:22]victim cache bank1 data memory 2bit ECC error; */
        unsigned int vcData11bEccMerr : 1; /* * [21:21]victim cache bank1 data memory 1bit ECC multi error; */
        unsigned int vcData11bEccErr : 1;  /* * [20:20]victim cache bank1 data memory 1bit ECC error; */
        unsigned int vcData02bEccMerr : 1; /* * [19:19]victim cache bank0 data memory 2bit ECC multi error; */
        unsigned int vcData02bEccErr : 1;  /* * [18:18]victim cache bank0 data memory 2bit ECC error; */
        unsigned int vcData01bEccMerr : 1; /* * [17:17]victim cache bank0 data memory 1bit ECC multi error; */
        unsigned int vcData01bEccErr : 1;  /* * [16:16]victim cache bank0 data memory 1bit ECC error; */
        unsigned int vcWb32bEccMerr : 1;   /* * [15:15]victim cache bank3 write back memory 2bit ECC multi error; */
        unsigned int vcWb32bEccErr : 1;    /* * [14:14]victim cache bank3 write back memory 2bit ECC error; */
        unsigned int vcWb31bEccMerr : 1;   /* * [13:13]victim cache bank3 write back memory 1bit ECC multi error; */
        unsigned int vcWb31bEccErr : 1;    /* * [12:12]victim cache bank3 write back memory 1bit ECC error; */
        unsigned int vcWb22bEccMerr : 1;   /* * [11:11]victim cache bank2 write back memory 2bit ECC multi error; */
        unsigned int vcWb22bEccErr : 1;    /* * [10:10]victim cache bank2 write back memory 2bit ECC error; */
        unsigned int vcWb21bEccMerr : 1;   /* * [9:9]victim cache bank2 write back memory 1bit ECC multi error; */
        unsigned int vcWb21bEccErr : 1;    /* * [8:8]victim cache bank2 write back memory 1bit ECC error; */
        unsigned int vcWb12bEccMerr : 1;   /* * [7:7]victim cache bank1 write back memory 2bit ECC multi error; */
        unsigned int vcWb12bEccErr : 1;    /* * [6:6]victim cache bank1 write back memory 2bit ECC error; */
        unsigned int vcWb11bEccMerr : 1;   /* * [5:5]victim cache bank1 write back memory 1bit ECC multi error; */
        unsigned int vcWb11bEccErr : 1;    /* * [4:4]victim cache bank1 write back memory 1bit ECC error; */
        unsigned int vcWb02bEccMerr : 1;   /* * [3:3]victim cache bank0 write back memory 2bit ECC multi error; */
        unsigned int vcWb02bEccErr : 1;    /* * [2:2]victim cache bank0 write back memory 2bit ECC error; */
        unsigned int vcWb01bEccMerr : 1;   /* * [1:1]victim cache bank0 write back memory 1bit ECC multi error; */
        unsigned int vcWb01bEccErr : 1;    /* * [0:0]victim cache bank0 write back memory 1bit ECC error; */
#else
        unsigned int vcWb01bEccErr : 1;    /* * [0:0]victim cache bank0 write back memory 1bit ECC error; */
        unsigned int vcWb01bEccMerr : 1;   /* * [1:1]victim cache bank0 write back memory 1bit ECC multi error; */
        unsigned int vcWb02bEccErr : 1;    /* * [2:2]victim cache bank0 write back memory 2bit ECC error; */
        unsigned int vcWb02bEccMerr : 1;   /* * [3:3]victim cache bank0 write back memory 2bit ECC multi error; */
        unsigned int vcWb11bEccErr : 1;    /* * [4:4]victim cache bank1 write back memory 1bit ECC error; */
        unsigned int vcWb11bEccMerr : 1;   /* * [5:5]victim cache bank1 write back memory 1bit ECC multi error; */
        unsigned int vcWb12bEccErr : 1;    /* * [6:6]victim cache bank1 write back memory 2bit ECC error; */
        unsigned int vcWb12bEccMerr : 1;   /* * [7:7]victim cache bank1 write back memory 2bit ECC multi error; */
        unsigned int vcWb21bEccErr : 1;    /* * [8:8]victim cache bank2 write back memory 1bit ECC error; */
        unsigned int vcWb21bEccMerr : 1;   /* * [9:9]victim cache bank2 write back memory 1bit ECC multi error; */
        unsigned int vcWb22bEccErr : 1;    /* * [10:10]victim cache bank2 write back memory 2bit ECC error; */
        unsigned int vcWb22bEccMerr : 1;   /* * [11:11]victim cache bank2 write back memory 2bit ECC multi error; */
        unsigned int vcWb31bEccErr : 1;    /* * [12:12]victim cache bank3 write back memory 1bit ECC error; */
        unsigned int vcWb31bEccMerr : 1;   /* * [13:13]victim cache bank3 write back memory 1bit ECC multi error; */
        unsigned int vcWb32bEccErr : 1;    /* * [14:14]victim cache bank3 write back memory 2bit ECC error; */
        unsigned int vcWb32bEccMerr : 1;   /* * [15:15]victim cache bank3 write back memory 2bit ECC multi error; */
        unsigned int vcData01bEccErr : 1;  /* * [16:16]victim cache bank0 data memory 1bit ECC error; */
        unsigned int vcData01bEccMerr : 1; /* * [17:17]victim cache bank0 data memory 1bit ECC multi error; */
        unsigned int vcData02bEccErr : 1;  /* * [18:18]victim cache bank0 data memory 2bit ECC error; */
        unsigned int vcData02bEccMerr : 1; /* * [19:19]victim cache bank0 data memory 2bit ECC multi error; */
        unsigned int vcData11bEccErr : 1;  /* * [20:20]victim cache bank1 data memory 1bit ECC error; */
        unsigned int vcData11bEccMerr : 1; /* * [21:21]victim cache bank1 data memory 1bit ECC multi error; */
        unsigned int vcData12bEccErr : 1;  /* * [22:22]victim cache bank1 data memory 2bit ECC error; */
        unsigned int vcData12bEccMerr : 1; /* * [23:23]victim cache bank1 data memory 2bit ECC multi error; */
        unsigned int vcData21bEccErr : 1;  /* * [24:24]victim cache bank2 data memory 1bit ECC error; */
        unsigned int vcData21bEccMerr : 1; /* * [25:25]victim cache bank2 data memory 1bit ECC multi error; */
        unsigned int vcData22bEccErr : 1;  /* * [26:26]victim cache bank2 data memory 2bit ECC error; */
        unsigned int vcData22bEccMerr : 1; /* * [27:27]victim cache bank2 data memory 2bit ECC multi error; */
        unsigned int vcData31bEccErr : 1;  /* * [28:28]victim cache bank3 data memory 1bit ECC error; */
        unsigned int vcData31bEccMerr : 1; /* * [29:29]victim cache bank3 data memory 1bit ECC multi error; */
        unsigned int vcData32bEccErr : 1;  /* * [30:30]victim cache bank3 data memory 2bit ECC error; */
        unsigned int vcData32bEccMerr : 1; /* * [31:31]victim cache bank3 data memory 2bit ECC multi error; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_VC_CACHE_ERR_U;

/* **
 * Union name :    SMMC_F_VC_CACHE_MASK
 * @brief
 * Description:
 */
typedef union tagUnSmmcFVcCacheMask {
    struct tagStSmmcFVcCacheMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16;           /* * [31:16]reserved. */
        unsigned int vcData32bEccErrMask : 1; /* * [15:15] */
        unsigned int vcData31bEccErrMask : 1; /* * [14:14] */
        unsigned int vcData22bEccErrMask : 1; /* * [13:13] */
        unsigned int vcData21bEccErrMask : 1; /* * [12:12] */
        unsigned int vcData12bEccErrMask : 1; /* * [11:11] */
        unsigned int vcData11bEccErrMask : 1; /* * [10:10] */
        unsigned int vcData02bEccErrMask : 1; /* * [9:9] */
        unsigned int vcData01bEccErrMask : 1; /* * [8:8] */
        unsigned int vcWb32bEccErrMask : 1;   /* * [7:7] */
        unsigned int vcWb31bEccErrMask : 1;   /* * [6:6] */
        unsigned int vcWb22bEccErrMask : 1;   /* * [5:5] */
        unsigned int vcWb21bEccErrMask : 1;   /* * [4:4] */
        unsigned int vcWb12bEccErrMask : 1;   /* * [3:3] */
        unsigned int vcWb11bEccErrMask : 1;   /* * [2:2] */
        unsigned int vcWb02bEccErrMask : 1;   /* * [1:1] */
        unsigned int vcWb01bEccErrMask : 1;   /* * [0:0] */
#else
        unsigned int vcWb01bEccErrMask : 1;   /* * [0:0] */
        unsigned int vcWb02bEccErrMask : 1;   /* * [1:1] */
        unsigned int vcWb11bEccErrMask : 1;   /* * [2:2] */
        unsigned int vcWb12bEccErrMask : 1;   /* * [3:3] */
        unsigned int vcWb21bEccErrMask : 1;   /* * [4:4] */
        unsigned int vcWb22bEccErrMask : 1;   /* * [5:5] */
        unsigned int vcWb31bEccErrMask : 1;   /* * [6:6] */
        unsigned int vcWb32bEccErrMask : 1;   /* * [7:7] */
        unsigned int vcData01bEccErrMask : 1; /* * [8:8] */
        unsigned int vcData02bEccErrMask : 1; /* * [9:9] */
        unsigned int vcData11bEccErrMask : 1; /* * [10:10] */
        unsigned int vcData12bEccErrMask : 1; /* * [11:11] */
        unsigned int vcData21bEccErrMask : 1; /* * [12:12] */
        unsigned int vcData22bEccErrMask : 1; /* * [13:13] */
        unsigned int vcData31bEccErrMask : 1; /* * [14:14] */
        unsigned int vcData32bEccErrMask : 1; /* * [15:15] */
        unsigned int reserved : 16;           /* * [31:16]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_VC_CACHE_MASK_U;

/* **
 * Union name :    SMMC_F_VC_CACHE_ERR_INFO
 * @brief
 * Description:
 */
typedef union tagUnSmmcFVcCacheErrInfo {
    struct tagStSmmcFVcCacheErrInfo {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int vcCacheErrInfo : 32; /* * [31:0][31:14]:reserved.If write back memory and data memory ECC error at
                                      the same time, here capture write back memory.If multi bank memory ECC error, here
                                      capture th e lowest bank.[13:12]: bank id.  2'b00: bank 0,  2'b01: bank 1,  2'b10:
                                      bank 2,  2'b11: bank 3. [11]: information type. indicate which buffer memory has
                                      ECC err or.  1'b0: write back memory;  1'b1: vc data memory; For victim cache wb
                                      memory error:[10:8] reserved.[7] error type:     1'b0: 1-bit ECC error.     1'b1:
                                      2-bit ECC error.[6:2] memory access index;[1:0] The error 16B position in 64B. For
                                      victim cache data memory error:[10] error type:     1'b0: 1-bit ECC error.     1'
                                      b1: 2-bit ECC error.[9:2] memory access index;[1:0] The error 16B position in 64B.
                                       */
#else
        unsigned int vcCacheErrInfo : 32; /* * [31:0][31:14]:reserved.If write back memory and data memory ECC error at
                                      the same time, here capture write back memory.If multi bank memory ECC error, here
                                      capture th e lowest bank.[13:12]: bank id.  2'b00: bank 0,  2'b01: bank 1,  2'b10:
                                      bank 2,  2'b11: bank 3. [11]: information type. indicate which buffer memory has
                                      ECC err or.  1'b0: write back memory;  1'b1: vc data memory; For victim cache wb
                                      memory error:[10:8] reserved.[7] error type:     1'b0: 1-bit ECC error.     1'b1:
                                      2-bit ECC error.[6:2] memory access index;[1:0] The error 16B position in 64B. For
                                      victim cache data memory error:[10] error type:     1'b0: 1-bit ECC error.     1'
                                      b1: 2-bit ECC error.[9:2] memory access index;[1:0] The error 16B position in 64B.
                                       */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_VC_CACHE_ERR_INFO_U;

/* **
 * Union name :    SMMC_F_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmmcFIndrectCtrl {
    struct tagStSmmcFIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
        unsigned int smmcFIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smmcFIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int
            smmcFIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'd0: main cache tag memory;data
                            structure:{ecc_bit(9bit),occupy(1bit),valid_bit(8bit),dirty_bit(4bit),stick_bit(1bit),host_
                            id(2bit),vf_id(10bit),gpa (56bit),o_bit(1bit),csize(2bit),tag_type(4bit),xid(40bit)}4'd1:
                            main cache data cache memory;4'd2: main cache VFA table;data structure
                            :{ecc_bit(7bit),pf_id(4bit),ft_enb(1bit),ft_pf_enb(1bit),rdma_enb(1bit),rdma_pf_enb(1bit),bat_ptr(18bit)}4'd3:
                            main cache recycle buffer;recycle buffer data str
                            ucture:{valid(1bit),head(1bit),tail(1bit),nxt_ptr(6),ready(1bit),early_retire(1bit),rf_done(1bit),cout_done(1bit),cla_bpc_flag(1bit),cla_entry_size(2bit),cla_xy
                            z(15bit),gpa_trans_flag(1bit),gpa_trans_lev(2bit),action_type(4),gpa_entry_idx(3),offset(6),tag_type(4bit),mem_idx_type(2bit),mem_idx(56bit),bank_id(2bit),cid0(
                            10bit),cid1(10bit),acc_size(5bit),error_flag(1bit),cache_line_size(2bit),base_cache_line_size(2bit),original_offset(6bit),api_src(3bit),opcode(4bit),api_token(3
                            8bit),cache_base_addr(10bit),qu_st_ack(1bit)}4'd4: main cache miss cam;miss cam data
                            structure: {occp_cid_idx(1bit),occp_way_idx(4bit),evt_way_idx(4bit),mem_idx
                            _type(2bit),mem_idx(56bit),offset(6bit),tag_type(4bit),original_tag_type(4bit),host_id(2bit),vf_id(10bit),xid(40bit),original_bank_id(2bit),original_cid0(10bit)
                            ,original_cid1(10bit),cla_lev(2bit),tail(1bit)};4'd5: main cache engine store data
                            buffer;4'd6: main cache QU store data buffer;4'd7: main cache QU store data b uffer free
                            list; data structure:{tag_head_address, tag_tail_address,tag_used_addr_num}.4'd8: main cache
                            refill data buffer; data structure:{control information( 3bit),refill data(128)}.4'd9:
                            victim cache request information;data
                            structure:{req_vld(1),req_otstag(6),pcie_template(6),req_type(3),req_size(6),host_id(2),vf_i
                            d(10),gpa_ofst(64),lcid(2),rsv(2)}4'd10: victim cache tag memory;data
                            structure:{tag_vld(1),dirty(4),host_id(2),vf_id(10),gpa(56),xid(40),type(4),csize(2)}4'd11
                            : victim cache data cache memory;4'd12: RTT latency counter;4'd13: virtual cache
                            configuration entries;4'd14: qu interface capture data flit AND smf refill erro r captured
                            information;refill error captured information data structure(83 bits in
                            total):{api_src(3),vf_id(10),api_opcode(4),api_tag_type(4),api_tag_sub_type(2
                            bit，如果是qu的请求，不需要看sub_type),gpa_translation_flag(1),
                            gpa_translation_lev(2),api_mem_index(56),captured_info_valid(1)};4'd15:direct wqe service
                            type mapping table AND refill timeout otstanding tag index.data structure:1)the mapping
                            table are total 64bits. each 2bit are a group, bit[1:0] is corresponding to service type 0
                            ,......bit[63:62] is corresponding to service type 31.bit[n+1 : n] = 2'b00, the service type
                            is L2NIC.bit[n+1 : n] = 2'b01, the service type is ROCE.bit[n+1 : n ] = 2'b10, the service
                            type is IWARP.2)refill timeout otstanding tag index:64bit, one bit corresponding to an
                            outstanding tag(bit0 corresponding to tag0; bit63 corresponding to tag63). when a tag is
                            timeout, the corresponding tag will be set, to inform SW which tag has encountered refill
                            timeout. The timeout tag will b e hanged up until the refill response return from host. */
        unsigned int
            smmcFIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote
                             0;以下软件间接访问的数据entry有些是大于32bit。软件写这些数据entry的时候需要发多次写操作，拼成一个完整的entry，然后由硬件一次写入memory中。硬件默认由entry的LSB开始写起（对应地址[2:0]=7）。软件读大于32b
                             it的entry时，对于一些较重要的控制信息在软件读地址[2:0]=7时，硬件锁存整个entry，后续读该entry时，从锁存寄存器中取。所以，综上所述，要求软件读/写以下数据时，地址[2:0]应该统一从7开始，由高到低依次操作。以下列出的memory的数据格式包含了ECC
                             bit，对于ECC bit，只可通过CSR间 接读；不可通过CSR间接写。It specifies memory address in one
                             group or internal address of the table.[20:3] memory access index field0) for main cache
                             tag memory[17:16] bank -ID[15] CID0/CID1 index type:1'b0:CID0;1'b1:CID1;[14:5] TAG memory
                             access index.       In SMF mode,[14:5] is tag group (include 4 tags) index in a memory
                             way.[4 :3]  tag num in a tag group0x0:0x2 - reserved 0x3:
                             data[159:128]([159:138]:reserved,[137:129]:ECC bit;[128]:tag data)0x4:  data[127:96]0x5:
                             data[95:64]0x6:  d ata[63:32]0x7:  data[31:0] 1) for main cache data cache memory:[21:20]
                             bank-ID[19] data memory coreesponding to CID0/CID1:1'b0:corresponding to CID0;1'b1:corres
                             ponding to CID1;[18:7] memory access index.       In SMF mode,[18:7] is 256Byte basic cache
                             line.[6:3]  16Byte data entry.0x0:0x2 - reserved 0x3:  data[159:128]
                             ([159:137]:reserved,[136:128]:ECC bit)0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x7:  data[31:0] 2) for main cache VFA table memory[12:3] memory index [2:0]
                             word select field0x0:0x6 - reserved 0x7:  data[31:0] ([31:26]:ECC bit;[25:0]:vfa data)3)
                             for main cache recycle buffer(only support for CSR read)[8:3] me mory access index.In SMF
                             mode, it's corresponding to 64 outstandings;[2:0]  word select field0x0:  reserved 0x1:
                             data[223:192]0x2:  data[191:160]0x3:  data[159 :128]0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x7:  data[31:0] 4) for main cache miss cam(only support for CSR read)[8:3]
                             memory access index.In SMF mode, it's corresponding to 64 outstandings;[2:0]  word select
                             field0x0:0x2 - reserved 0x3:  data[159:128]0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x 7:  data[31:0] 5) for main cache engine store data buffer(only support for
                             CSR read)[12] memory id:     0:stb0;     1:stb1;[11:6] memory access index.In SMF mod e,
                             it's in the unit of 64Byte, and corresponding to 64 outstandings;[5:3]  16Byte data entry
                             index in a 64Byte store data; When 0x4, indicate to access 1bit dir ty and 64bit byte
                             enable.[2:0]  word select field0x0:0x2 - reserved0x3:  data[159:128] 0x4:  data[127:96]0x5:
                             data[95:64]0x6:  data[63:32]0x7:  data[31:0] 6) f or main cache QU store data buffer(only
                             support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte,
                             and includes 256 of 64byte; [4: 3]  16Byte data entry index in a 64Byte data.[2:0]  word
                             select field0x0:0x2 - reserved 0x3:  data[159:128]([159:137]:reserved,[136:128]:ECC
                             bit)0x4:  data[127: 96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0]7) for mainc cache
                             QU store data buffer list(only support for CSR read)[8:3] memory access index.[2:0]  wor d
                             select field0x0:0x6 - reserved 0x7:  data[31:0] 8) for main cache refill data buffer(only
                             support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte,
                             and includes 256 of 64byte; [4:3]  16Byte data entry index in a 64Byte data.[2:0]  word
                             select field0x0:0x2 - reserved 0x3:  data[159:128]( [159:140]:reserved,[139:131]:ECC
                             bit,[130:129]:refill buffer entry control data)0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x7:  data[31:0] 9) victim c ache request information (only support for CSR
                             read)[4:3] victim cache bank ID;[2:0]  word select field0x0:0x3 - reserved 0x4:
                             data[127:96]0x5:  data[95:64]0x6 :  data[63:32]0x7:  data[31:0] 10) victim cache tag
                             memory(only support for CSR read,and CSR write
                             clear.注意CSR写清时，要没有writeback流量，否则可能造成错误。例如1KB的cacheline占4个256B
                             ，当逻辑写了2个256B时，CSR发起清操作，前面2个256B会被清掉，但后面2个256B不清。)[10:9]
                             victim cache bank ID.[8:3] memory access index.In SMF mode, there are 32 tags in each
                             victim cache.[2:0] word select field0x0:0x3 - reserved 0x4:  data[127:96]0x5:
                             data[95:64]0x6:  data[63:32]0x7:  data[31:0] 11) victim cache data cache memory(only
                             support for C SR read)[14:13] victim cache bank ID.[12:7] the memory access index. In SMF
                             mode, the victim cache is 256Byte in width.[6:3] the index number of eache 16Byte in
                              256Byte of cache line.[2:0]  word select field0x0:0x2 - reserved 0x3:  data[159:128] 0x4:
                             data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0] 12) R TT latency
                             counter(only support for CSR read)[3] select which counter to read:1'b1: longest letency
                             counter. 1'b0: shortest letency counter. [2:0]  word select field0x0~5: reserved.0x6:
                             counter[47:32].0x7: counter[31:0].13) virtual cache configuration entries[5:3] virtual
                             cache configuration entry number:3'd0: QU virtu al configure entry 0(RDMA parent
                             context).3'd1: QU virtual configure entry 1(flow based parent context).3'd2: QU virtual
                             configure entry 2(child context).3'd3: Direct WQE virtual configure entry 0(L2 NIC direct
                             WQE).3'd4: Direct WQE virtual configure entry 1(ROCE direct WQE).3'd5: Direct WQE virtual
                             configure entry 2(I WARP direct WQE).3'd6: CLA virtual configure entry.3'd7: MBaseAddr
                             configure [2:0]  word select field0x0~6: reserved.0x7: entry data[31:0].14) qu interface
                             capt ure data flit[4:3]: qu interface capture data entry number     2'b00: first captured
                             data flit sent from QU to SMMC_F;     2'b01: first captured data flit sent from SMMC_F to
                             QU;     2'b10: refill error captured information;[2:0]  word select field(Note:for refill
                             error captured information, word select field ONLY use 0x5~0x7,0x0~0x4 is reserved)0x0:0x2
                             - reserved 0x3:  data[159:128]0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:
                             data[31:0] 15) service type mapping table AND refill timeout outstanding tag index.[3]:
                             register entry select field1'b0: service type mapping table;1'b1: refill timeout
                             outstanding tag index (only support for CSR read).[2:0]  word select field0x0:0x5 -
                             reserved 0x6:  data[63:32]0x7:  data[31:0]
                              */
#else
        unsigned int
            smmcFIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote
                             0;以下软件间接访问的数据entry有些是大于32bit。软件写这些数据entry的时候需要发多次写操作，拼成一个完整的entry，然后由硬件一次写入memory中。硬件默认由entry的LSB开始写起（对应地址[2:0]=7）。软件读大于32b
                             it的entry时，对于一些较重要的控制信息在软件读地址[2:0]=7时，硬件锁存整个entry，后续读该entry时，从锁存寄存器中取。所以，综上所述，要求软件读/写以下数据时，地址[2:0]应该统一从7开始，由高到低依次操作。以下列出的memory的数据格式包含了ECC
                             bit，对于ECC bit，只可通过CSR间 接读；不可通过CSR间接写。It specifies memory address in one
                             group or internal address of the table.[20:3] memory access index field0) for main cache
                             tag memory[17:16] bank -ID[15] CID0/CID1 index type:1'b0:CID0;1'b1:CID1;[14:5] TAG memory
                             access index.       In SMF mode,[14:5] is tag group (include 4 tags) index in a memory
                             way.[4 :3]  tag num in a tag group0x0:0x2 - reserved 0x3:
                             data[159:128]([159:138]:reserved,[137:129]:ECC bit;[128]:tag data)0x4:  data[127:96]0x5:
                             data[95:64]0x6:  d ata[63:32]0x7:  data[31:0] 1) for main cache data cache memory:[21:20]
                             bank-ID[19] data memory coreesponding to CID0/CID1:1'b0:corresponding to CID0;1'b1:corres
                             ponding to CID1;[18:7] memory access index.       In SMF mode,[18:7] is 256Byte basic cache
                             line.[6:3]  16Byte data entry.0x0:0x2 - reserved 0x3:  data[159:128]
                             ([159:137]:reserved,[136:128]:ECC bit)0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x7:  data[31:0] 2) for main cache VFA table memory[12:3] memory index [2:0]
                             word select field0x0:0x6 - reserved 0x7:  data[31:0] ([31:26]:ECC bit;[25:0]:vfa data)3)
                             for main cache recycle buffer(only support for CSR read)[8:3] me mory access index.In SMF
                             mode, it's corresponding to 64 outstandings;[2:0]  word select field0x0:  reserved 0x1:
                             data[223:192]0x2:  data[191:160]0x3:  data[159 :128]0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x7:  data[31:0] 4) for main cache miss cam(only support for CSR read)[8:3]
                             memory access index.In SMF mode, it's corresponding to 64 outstandings;[2:0]  word select
                             field0x0:0x2 - reserved 0x3:  data[159:128]0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x 7:  data[31:0] 5) for main cache engine store data buffer(only support for
                             CSR read)[12] memory id:     0:stb0;     1:stb1;[11:6] memory access index.In SMF mod e,
                             it's in the unit of 64Byte, and corresponding to 64 outstandings;[5:3]  16Byte data entry
                             index in a 64Byte store data; When 0x4, indicate to access 1bit dir ty and 64bit byte
                             enable.[2:0]  word select field0x0:0x2 - reserved0x3:  data[159:128] 0x4:  data[127:96]0x5:
                             data[95:64]0x6:  data[63:32]0x7:  data[31:0] 6) f or main cache QU store data buffer(only
                             support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte,
                             and includes 256 of 64byte; [4: 3]  16Byte data entry index in a 64Byte data.[2:0]  word
                             select field0x0:0x2 - reserved 0x3:  data[159:128]([159:137]:reserved,[136:128]:ECC
                             bit)0x4:  data[127: 96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0]7) for mainc cache
                             QU store data buffer list(only support for CSR read)[8:3] memory access index.[2:0]  wor d
                             select field0x0:0x6 - reserved 0x7:  data[31:0] 8) for main cache refill data buffer(only
                             support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte,
                             and includes 256 of 64byte; [4:3]  16Byte data entry index in a 64Byte data.[2:0]  word
                             select field0x0:0x2 - reserved 0x3:  data[159:128]( [159:140]:reserved,[139:131]:ECC
                             bit,[130:129]:refill buffer entry control data)0x4:  data[127:96]0x5:  data[95:64]0x6:
                             data[63:32]0x7:  data[31:0] 9) victim c ache request information (only support for CSR
                             read)[4:3] victim cache bank ID;[2:0]  word select field0x0:0x3 - reserved 0x4:
                             data[127:96]0x5:  data[95:64]0x6 :  data[63:32]0x7:  data[31:0] 10) victim cache tag
                             memory(only support for CSR read,and CSR write
                             clear.注意CSR写清时，要没有writeback流量，否则可能造成错误。例如1KB的cacheline占4个256B
                             ，当逻辑写了2个256B时，CSR发起清操作，前面2个256B会被清掉，但后面2个256B不清。)[10:9]
                             victim cache bank ID.[8:3] memory access index.In SMF mode, there are 32 tags in each
                             victim cache.[2:0] word select field0x0:0x3 - reserved 0x4:  data[127:96]0x5:
                             data[95:64]0x6:  data[63:32]0x7:  data[31:0] 11) victim cache data cache memory(only
                             support for C SR read)[14:13] victim cache bank ID.[12:7] the memory access index. In SMF
                             mode, the victim cache is 256Byte in width.[6:3] the index number of eache 16Byte in
                              256Byte of cache line.[2:0]  word select field0x0:0x2 - reserved 0x3:  data[159:128] 0x4:
                             data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:  data[31:0] 12) R TT latency
                             counter(only support for CSR read)[3] select which counter to read:1'b1: longest letency
                             counter. 1'b0: shortest letency counter. [2:0]  word select field0x0~5: reserved.0x6:
                             counter[47:32].0x7: counter[31:0].13) virtual cache configuration entries[5:3] virtual
                             cache configuration entry number:3'd0: QU virtu al configure entry 0(RDMA parent
                             context).3'd1: QU virtual configure entry 1(flow based parent context).3'd2: QU virtual
                             configure entry 2(child context).3'd3: Direct WQE virtual configure entry 0(L2 NIC direct
                             WQE).3'd4: Direct WQE virtual configure entry 1(ROCE direct WQE).3'd5: Direct WQE virtual
                             configure entry 2(I WARP direct WQE).3'd6: CLA virtual configure entry.3'd7: MBaseAddr
                             configure [2:0]  word select field0x0~6: reserved.0x7: entry data[31:0].14) qu interface
                             capt ure data flit[4:3]: qu interface capture data entry number     2'b00: first captured
                             data flit sent from QU to SMMC_F;     2'b01: first captured data flit sent from SMMC_F to
                             QU;     2'b10: refill error captured information;[2:0]  word select field(Note:for refill
                             error captured information, word select field ONLY use 0x5~0x7,0x0~0x4 is reserved)0x0:0x2
                             - reserved 0x3:  data[159:128]0x4:  data[127:96]0x5:  data[95:64]0x6:  data[63:32]0x7:
                             data[31:0] 15) service type mapping table AND refill timeout outstanding tag index.[3]:
                             register entry select field1'b0: service type mapping table;1'b1: refill timeout
                             outstanding tag index (only support for CSR read).[2:0]  word select field0x0:0x5 -
                             reserved 0x6:  data[63:32]0x7:  data[31:0]
                              */
        unsigned int
            smmcFIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'd0: main cache tag memory;data
                            structure:{ecc_bit(9bit),occupy(1bit),valid_bit(8bit),dirty_bit(4bit),stick_bit(1bit),host_
                            id(2bit),vf_id(10bit),gpa (56bit),o_bit(1bit),csize(2bit),tag_type(4bit),xid(40bit)}4'd1:
                            main cache data cache memory;4'd2: main cache VFA table;data structure
                            :{ecc_bit(7bit),pf_id(4bit),ft_enb(1bit),ft_pf_enb(1bit),rdma_enb(1bit),rdma_pf_enb(1bit),bat_ptr(18bit)}4'd3:
                            main cache recycle buffer;recycle buffer data str
                            ucture:{valid(1bit),head(1bit),tail(1bit),nxt_ptr(6),ready(1bit),early_retire(1bit),rf_done(1bit),cout_done(1bit),cla_bpc_flag(1bit),cla_entry_size(2bit),cla_xy
                            z(15bit),gpa_trans_flag(1bit),gpa_trans_lev(2bit),action_type(4),gpa_entry_idx(3),offset(6),tag_type(4bit),mem_idx_type(2bit),mem_idx(56bit),bank_id(2bit),cid0(
                            10bit),cid1(10bit),acc_size(5bit),error_flag(1bit),cache_line_size(2bit),base_cache_line_size(2bit),original_offset(6bit),api_src(3bit),opcode(4bit),api_token(3
                            8bit),cache_base_addr(10bit),qu_st_ack(1bit)}4'd4: main cache miss cam;miss cam data
                            structure: {occp_cid_idx(1bit),occp_way_idx(4bit),evt_way_idx(4bit),mem_idx
                            _type(2bit),mem_idx(56bit),offset(6bit),tag_type(4bit),original_tag_type(4bit),host_id(2bit),vf_id(10bit),xid(40bit),original_bank_id(2bit),original_cid0(10bit)
                            ,original_cid1(10bit),cla_lev(2bit),tail(1bit)};4'd5: main cache engine store data
                            buffer;4'd6: main cache QU store data buffer;4'd7: main cache QU store data b uffer free
                            list; data structure:{tag_head_address, tag_tail_address,tag_used_addr_num}.4'd8: main cache
                            refill data buffer; data structure:{control information( 3bit),refill data(128)}.4'd9:
                            victim cache request information;data
                            structure:{req_vld(1),req_otstag(6),pcie_template(6),req_type(3),req_size(6),host_id(2),vf_i
                            d(10),gpa_ofst(64),lcid(2),rsv(2)}4'd10: victim cache tag memory;data
                            structure:{tag_vld(1),dirty(4),host_id(2),vf_id(10),gpa(56),xid(40),type(4),csize(2)}4'd11
                            : victim cache data cache memory;4'd12: RTT latency counter;4'd13: virtual cache
                            configuration entries;4'd14: qu interface capture data flit AND smf refill erro r captured
                            information;refill error captured information data structure(83 bits in
                            total):{api_src(3),vf_id(10),api_opcode(4),api_tag_type(4),api_tag_sub_type(2
                            bit，如果是qu的请求，不需要看sub_type),gpa_translation_flag(1),
                            gpa_translation_lev(2),api_mem_index(56),captured_info_valid(1)};4'd15:direct wqe service
                            type mapping table AND refill timeout otstanding tag index.data structure:1)the mapping
                            table are total 64bits. each 2bit are a group, bit[1:0] is corresponding to service type 0
                            ,......bit[63:62] is corresponding to service type 31.bit[n+1 : n] = 2'b00, the service type
                            is L2NIC.bit[n+1 : n] = 2'b01, the service type is ROCE.bit[n+1 : n ] = 2'b10, the service
                            type is IWARP.2)refill timeout otstanding tag index:64bit, one bit corresponding to an
                            outstanding tag(bit0 corresponding to tag0; bit63 corresponding to tag63). when a tag is
                            timeout, the corresponding tag will be set, to inform SW which tag has encountered refill
                            timeout. The timeout tag will b e hanged up until the refill response return from host. */
        unsigned int smmcFIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smmcFIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smmcFIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_INDRECT_CTRL_U;

/* **
 * Union name :    SMMC_F_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmmcFIndrectTimeout {
    struct tagStSmmcFIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smmcFIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMMC_F_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmmcFIndrectData {
    struct tagStSmmcFIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write:
                                       Software write data to these registes and then enable indirect access, logic will
                                       send these data to target.When operation read:  Logic write data to these
                                       registers and refresh xxx_indir_stat, software will get these data from target.
                                       */
#else
        unsigned int smmcFIndirData : 32;    /* * [31:0]It specifies the indirect access data:When operation write:
                                          Software write data to these registes and then enable indirect access, logic will
                                          send these data to target.When operation read:  Logic write data to these
                                          registers and refresh xxx_indir_stat, software will get these data from target.
                                          */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_INDRECT_DATA_U;

/* **
 * Union name :    SMMC_F_MC_CNT_ENB
 * @brief               counter enable
 * Description:
 */
typedef union tagUnSmmcFMcCntEnb {
    struct tagStSmmcFMcCntEnb {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 24;     /* * [31:8]reserved. */
        unsigned int smmcFMcCntEnb : 8; /* * [7:0]SMMC main cache counter enable.1'b0: disable SMMC counter.1'b1: enable
                                         * SMMC counter.
                                         */
#else
        unsigned int smmcFMcCntEnb : 8; /* * [7:0]SMMC main cache counter enable.1'b0: disable SMMC counter.1'b1: enable
                                         * SMMC counter.
                                         */
        unsigned int reserved : 24;     /* * [31:8]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_ENB_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0
 * @brief               counter event selection enable
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSelEnbGrp0 {
    struct tagStSmmcFMcCntEventSelEnbGrp0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFMcCntEventSelEnb3 : 8; /* * [31:24]SMMC counter3 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb2 : 8; /* * [23:16]SMMC counter2 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb1 : 8; /* * [15:8]SMMC counter1 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb0 : 8; /* * [7:0]SMMC counter0 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
#else
        unsigned int smmcFMcCntEventSelEnb0 : 8; /* * [7:0]SMMC counter0 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb1 : 8; /* * [15:8]SMMC counter1 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb2 : 8; /* * [23:16]SMMC counter2 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb3 : 8; /* * [31:24]SMMC counter3 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1
 * @brief               counter event selection enable
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSelEnbGrp1 {
    struct tagStSmmcFMcCntEventSelEnbGrp1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFMcCntEventSelEnb7 : 8; /* * [31:24]SMMC counter7 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb6 : 8; /* * [23:16]SMMC counter6 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb5 : 8; /* * [15:8]SMMC counter5 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb4 : 8; /* * [7:0]SMMC counter4 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
#else
        unsigned int smmcFMcCntEventSelEnb4 : 8; /* * [7:0]SMMC counter4 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb5 : 8; /* * [15:8]SMMC counter5 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb6 : 8; /* * [23:16]SMMC counter6 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
        unsigned int smmcFMcCntEventSelEnb7 : 8; /* * [31:24]SMMC counter7 event configuration enable.If one bit of this
                                              signal is valid, the corresponding event is valid. And counter0 is
                                              configured to counter these corre ponding events.A counter can be
                                              configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API
                                              type;3: command source;2: bank-ID;1: tag type;0: VF-ID
                                              ; */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL0
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel0 {
    struct tagStSmmcFMcCntEventSel0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel0UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel0EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel0ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel0ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel0BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel0TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel0VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel0VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel0TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel0BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel0ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel0ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel0EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel0UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL0_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL1
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel1 {
    struct tagStSmmcFMcCntEventSel1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel1UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel1EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel1ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel1ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel1BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel1TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel1VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel1VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel1TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel1BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel1ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel1ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel1EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel1UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL1_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL2
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel2 {
    struct tagStSmmcFMcCntEventSel2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel2UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel2EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel2ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel2ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel2BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel2TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel2VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel2VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel2TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel2BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel2ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel2ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel2EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel2UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL2_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL3
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel3 {
    struct tagStSmmcFMcCntEventSel3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel3UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel3EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel3ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel3ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel3BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel3TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel3VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel3VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel3TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel3BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel3ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel3ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel3EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel3UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL3_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL4
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel4 {
    struct tagStSmmcFMcCntEventSel4 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel4UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel4EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel4ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel4ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel4BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel4TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel4VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel4VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel4TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel4BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel4ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel4ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel4EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel4UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL4_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL5
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel5 {
    struct tagStSmmcFMcCntEventSel5 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel5UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel5EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel5ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel5ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel5BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel5TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel5VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel5VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel5TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel5BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel5ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel5ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel5EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel5UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL5_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL6
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel6 {
    struct tagStSmmcFMcCntEventSel6 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel6UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel6EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel6ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel6ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel6BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel6TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel6VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel6VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel6TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel6BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel6ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel6ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel6EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel6UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL6_U;

/* **
 * Union name :    SMMC_F_MC_CNT_EVENT_SEL7
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCntEventSel7 {
    struct tagStSmmcFMcCntEventSel7 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int mcCntEventSel7UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
        unsigned int
            mcCntEventSel7EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel7ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int mcCntEventSel7ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel7BankId : 2;  /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                             enabled, the counter only counts for requests in a specific bank.2’b00:
                                             bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel7TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count
                                                 * for. If enabled, the counter only counts for requests that accessing
                                                 * a specific type of table.
                                                 */
        unsigned int reserved : 5;              /* * [14:10]reserved */
        unsigned int mcCntEventSel7VfId : 10;   /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                 * only counts for requests belong to a specific VF_ID.
                                                 */
#else
        unsigned int mcCntEventSel7VfId : 10;    /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter
                                                  * only counts for requests belong to a specific VF_ID.
                                                  */
        unsigned int reserved : 5;               /* * [14:10]reserved */
        unsigned int mcCntEventSel7TagType : 4;  /* * [18:15]tag typeConfigure which types of table in cache to count
                                                  * for. If enabled, the counter only counts for requests that accessing
                                                  * a specific type of table.
                                                  */
        unsigned int mcCntEventSel7BankId : 2;   /* * [20:19]bank-ID.Configure which bank of cache to count for. If
                                              enabled, the counter only counts for requests in a specific bank.2’b00:
                                              bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */
        unsigned int mcCntEventSel7ReqSrc : 3;  /* * [23:21]Configure which source of requests to count for. If enabled,
                                             the counter only counts for requests that come from a specific
                                             source.3’b000: SMLC0;3’b001: SMLC1;3
                                             ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */
        unsigned int mcCntEventSel7ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled,
                                             the counter only counts for a specific type of request.4'b0000 normal
                                             load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100
                                             store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load
                                             memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */
        unsigned int
            mcCntEventSel7EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter
                                     only counts for a specific type of event. This field must be configured enable,
                                     when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number
                                     that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for
                                     the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache
                                     pipeline. For a whole request from engine or QU, it may be scheduled into the main
                                     cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache
                                     miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache
                                     miss）。Count for how many requests have encounter cache miss.3’b011: 统计main
                                     cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for
                                     the number that main cache issues refill requests to victim cache.3’b100: 统计main
                                     cache从C PI收到refill response的次数（默认），或者统计refill data
                                     size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC.
                                     It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main
                                     cache向victim cache发起write back操作的次数（默认以cache line
                                     为单位），或者统计write back data size（以64Byte为单位）。Count for the number of
                                     evict ing from main cache to victim cache. It can be counted in the unit of times
                                     or in the unit of (64byte).3’b110: 统计cache miss后在main
                                     cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a
                                     request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main
                                     cache中first issue就Hit的API个数。Counter for the number of
                                      requests that cache hit and finish in the first issue loop. */
        unsigned int mcCntEventSel7UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to
                                              enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only
                                              used to count refill or write back data size); */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CNT_EVENT_SEL7_U;

/* **
 * Union name :    SMMC_F_MC_STATUS
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcStatus {
    struct tagStSmmcFMcStatus {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 21;     /* * [31:11] */
        unsigned int smmcRfTimeout : 1; /* * [10:10]indicate there is outstanding tag timeout in SMMC, when refill data
                                     from CPI. This signal could not tell which outstanding tag is timeout in SMMC. SW
                                     should rea d RCB of each outstanding tag to check out which outstanding tag is
                                     timeout. */
        unsigned int quTxFlitCtpDone : 1; /* * [9:9]QU transmit data flit capture done. When this signal is valid, SW
                                           * can read captured data flit via CSR.1: capture done;0: capturing;
                                           */
        unsigned int quRxFlitCtpDone : 1; /* * [8:8]QU received data flit capture done. When this signal is valid, SW
                                           * can read captured data flit via CSR.1: capture done;0: capturing;
                                           */
        unsigned int mcFreeTagNum : 7;    /* * [7:1]the free outstanding tag number in SMMC */
        unsigned int mcInitDone : 1; /* * [0:0]smmc initial done signal.1: initial done;0: in initial processing or have
                                      * not started initial processing.
                                      */
#else
        unsigned int mcInitDone : 1; /* * [0:0]smmc initial done signal.1: initial done;0: in initial processing or have
                                      * not started initial processing.
                                      */
        unsigned int mcFreeTagNum : 7;    /* * [7:1]the free outstanding tag number in SMMC */
        unsigned int quRxFlitCtpDone : 1; /* * [8:8]QU received data flit capture done. When this signal is valid, SW
                                           * can read captured data flit via CSR.1: capture done;0: capturing;
                                           */
        unsigned int quTxFlitCtpDone : 1; /* * [9:9]QU transmit data flit capture done. When this signal is valid, SW
                                           * can read captured data flit via CSR.1: capture done;0: capturing;
                                           */
        unsigned int smmcRfTimeout : 1; /* * [10:10]indicate there is outstanding tag timeout in SMMC, when refill data
                                     from CPI. This signal could not tell which outstanding tag is timeout in SMMC. SW
                                     should rea d RCB of each outstanding tag to check out which outstanding tag is
                                     timeout. */
        unsigned int reserved : 21;     /* * [31:11] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_STATUS_U;

/* **
* Union name :    SMMC_F_MC_CNT0
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB0 and SMMC_F_MC_CNT_EVENT_SEL0.

* Description:
*/
typedef union tagUnSmmcFMcCnt0 {
    struct tagStSmmcFMcCnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt0 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt0 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT0_U;

/* **
* Union name :    SMMC_F_MC_CNT1
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB1 and SMMC_F_MC_CNT_EVENT_SEL1.

* Description:
*/
typedef union tagUnSmmcFMcCnt1 {
    struct tagStSmmcFMcCnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt1 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt1 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT1_U;

/* **
* Union name :    SMMC_F_MC_CNT2
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB2 and SMMC_F_MC_CNT_EVENT_SEL2.

* Description:
*/
typedef union tagUnSmmcFMcCnt2 {
    struct tagStSmmcFMcCnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt2 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt2 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT2_U;

/* **
* Union name :    SMMC_F_MC_CNT3
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB3 and SMMC_F_MC_CNT_EVENT_SEL3.

* Description:
*/
typedef union tagUnSmmcFMcCnt3 {
    struct tagStSmmcFMcCnt3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt3 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt3 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT3_U;

/* **
* Union name :    SMMC_F_MC_CNT4
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB4 and SMMC_F_MC_CNT_EVENT_SEL4.

* Description:
*/
typedef union tagUnSmmcFMcCnt4 {
    struct tagStSmmcFMcCnt4 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt4 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt4 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT4_U;

/* **
* Union name :    SMMC_F_MC_CNT5
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB5 and SMMC_F_MC_CNT_EVENT_SEL5.

* Description:
*/
typedef union tagUnSmmcFMcCnt5 {
    struct tagStSmmcFMcCnt5 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt5 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt5 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT5_U;

/* **
* Union name :    SMMC_F_MC_CNT6
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB6 and SMMC_F_MC_CNT_EVENT_SEL6.

* Description:
*/
typedef union tagUnSmmcFMcCnt6 {
    struct tagStSmmcFMcCnt6 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt6 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt6 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT6_U;

/* **
* Union name :    SMMC_F_MC_CNT7
* @brief               This SMMC main cache counter0 register is a dynamic counter to count any event that is configured
by SMMC_F_MC_CNT_EVENT_SEL_ENB7 and SMMC_F_MC_CNT_EVENT_SEL7.

* Description:
*/
typedef union tagUnSmmcFMcCnt7 {
    struct tagStSmmcFMcCnt7 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
        unsigned long long smmcFMcCnt7 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
#else
        unsigned long long smmcFMcCnt7 : 48; /* * [47:0]This can be programmed to count any event depeding on the
                                                configuration. */
        unsigned long long reserved : 16;    /* * [63:48]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned long long ullValue;
} CSR_SMMC_F_MC_CNT7_U;

/* **
 * Union name :    SMMC_F_VC_FIFO_DEPTH0
 * @brief               SMMC_F victim cache FIFO depth or   credit
 * Description:
 */
typedef union tagUnSmmcFVcFifoDepth0 {
    struct tagStSmmcFVcFifoDepth0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int vc3WbCtrlFifoDepth : 3; /* * [31:29]Bank3 victim cache write back control fifo real depth. */
        unsigned int vc2WbCtrlFifoDepth : 3; /* * [28:26]Bank2 victim cache write back control fifo real depth. */
        unsigned int vc1WbCtrlFifoDepth : 3; /* * [25:23]Bank1 victim cache write back control fifo real depth. */
        unsigned int vc0WbCtrlFifoDepth : 3; /* * [22:20]Bank0 victim cache write back control fifo real depth.The write
                                              * back control fifo is between MC and VC, the total depth is 6.
                                              */
        unsigned int vc3WbDataFifoDepth : 5; /* * [19:15]Bank3 victim cache write back data fifo real depth. */
        unsigned int vc2WbDataFifoDepth : 5; /* * [14:10]Bank2 victim cache write back data fifo real depth. */
        unsigned int vc1WbDataFifoDepth : 5; /* * [9:5]Bank1 victim cache write back data fifo real depth. */
        unsigned int vc0WbDataFifoDepth : 5; /* * [4:0]Bank0 victim cache write back data fifo real depth.The write back
                                              * data fifo is between MC and VC, the total depth is 24. The data fifo
                                              * contain 24 x64B.
                                              */
#else
        unsigned int vc0WbDataFifoDepth : 5; /* * [4:0]Bank0 victim cache write back data fifo real depth.The write back
                                              * data fifo is between MC and VC, the total depth is 24. The data fifo
                                              * contain 24 x64B.
                                              */
        unsigned int vc1WbDataFifoDepth : 5; /* * [9:5]Bank1 victim cache write back data fifo real depth. */
        unsigned int vc2WbDataFifoDepth : 5; /* * [14:10]Bank2 victim cache write back data fifo real depth. */
        unsigned int vc3WbDataFifoDepth : 5; /* * [19:15]Bank3 victim cache write back data fifo real depth. */
        unsigned int vc0WbCtrlFifoDepth : 3; /* * [22:20]Bank0 victim cache write back control fifo real depth.The write
                                              * back control fifo is between MC and VC, the total depth is 6.
                                              */
        unsigned int vc1WbCtrlFifoDepth : 3; /* * [25:23]Bank1 victim cache write back control fifo real depth. */
        unsigned int vc2WbCtrlFifoDepth : 3; /* * [28:26]Bank2 victim cache write back control fifo real depth. */
        unsigned int vc3WbCtrlFifoDepth : 3; /* * [31:29]Bank3 victim cache write back control fifo real depth. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_VC_FIFO_DEPTH0_U;

/* **
 * Union name :    SMMC_F_VC_FIFO_DEPTH1
 * @brief               SMMC_F victim cache FIFO depth or   credit
 * Description:
 */
typedef union tagUnSmmcFVcFifoDepth1 {
    struct tagStSmmcFVcFifoDepth1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 7;         /* * [31:25] */
        unsigned int vcCrdtFromSmit : 3;   /* * [24:22]credit counter from SMIT.The initial value is 6. */
        unsigned int smxtfFifoDepth : 6;   /* * [21:16]smxt interface fifo.The fifo total depth is 32. */
        unsigned int vc3DataFifoDepth : 2; /* * [15:14]Bank3 victim cache data fifo real depth. */
        unsigned int vc2DataFifoDepth : 2; /* * [13:12]Bank2 victim cache data fifo real depth. */
        unsigned int vc1DataFifoDepth : 2; /* * [11:10]Bank1 victim cache data fifo real depth. */
        unsigned int vc0DataFifoDepth : 2; /* * [9:8]Bank0 victim cache data fifo real depth.This fifo is between each
                                        vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are
                                        muxed to 1 input i nto smxt_intf. */
        unsigned int vc3CtrlFifoDepth : 2; /* * [7:6]Bank3 victim cache control fifo real depth. */
        unsigned int vc2CtrlFifoDepth : 2; /* * [5:4]Bank2 victim cache control fifo real depth. */
        unsigned int vc1CtrlFifoDepth : 2; /* * [3:2]Bank1 victim cache control fifo real depth. */
        unsigned int vc0CtrlFifoDepth : 2; /* * [1:0]Bank0 victim cache control fifo real depth.This fifo is between
                                        each vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are
                                        muxed to 1 inpu t into smxt_intf. */
#else
        unsigned int vc0CtrlFifoDepth : 2;   /* * [1:0]Bank0 victim cache control fifo real depth.This fifo is between
                                          each vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are
                                          muxed to 1 inpu t into smxt_intf. */
        unsigned int vc1CtrlFifoDepth : 2;   /* * [3:2]Bank1 victim cache control fifo real depth. */
        unsigned int vc2CtrlFifoDepth : 2;   /* * [5:4]Bank2 victim cache control fifo real depth. */
        unsigned int vc3CtrlFifoDepth : 2;   /* * [7:6]Bank3 victim cache control fifo real depth. */
        unsigned int vc0DataFifoDepth : 2;   /* * [9:8]Bank0 victim cache data fifo real depth.This fifo is between each
                                          vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are
                                          muxed to 1 input i nto smxt_intf. */
        unsigned int vc1DataFifoDepth : 2;   /* * [11:10]Bank1 victim cache data fifo real depth. */
        unsigned int vc2DataFifoDepth : 2;   /* * [13:12]Bank2 victim cache data fifo real depth. */
        unsigned int vc3DataFifoDepth : 2;   /* * [15:14]Bank3 victim cache data fifo real depth. */
        unsigned int smxtfFifoDepth : 6;     /* * [21:16]smxt interface fifo.The fifo total depth is 32. */
        unsigned int vcCrdtFromSmit : 3;     /* * [24:22]credit counter from SMIT.The initial value is 6. */
        unsigned int reserved : 7;           /* * [31:25] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_VC_FIFO_DEPTH1_U;

/* **
 * Union name :    SMMC_F_MC_FIFO1_DEPTH
 * @brief               SMMC_F main cache FIFO depth or   credit
 * Description:
 */
typedef union tagUnSmmcFMcFifo1Depth {
    struct tagStSmmcFMcFifo1Depth {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 3;         /* * [31:29] */
        unsigned int lrb2FifoDepth : 5;    /* * [28:24]lrb2 fifo real depth. */
        unsigned int lrb1FifoDepth : 5;    /* * [23:19]lrb1 fifo real depth. */
        unsigned int lrb0FifoDepth : 5;    /* * [18:14]lrb0 fifo real depth. */
        unsigned int quDataFifoDepth : 6;  /* * [13:8]QU data fifo real depth. */
        unsigned int quCmdFifoDepth : 4;   /* * [7:4]QU command fifo real depth. */
        unsigned int dataCreditFromQu : 4; /* * [3:0]data credit from QU. */
#else
        unsigned int dataCreditFromQu : 4;   /* * [3:0]data credit from QU. */
        unsigned int quCmdFifoDepth : 4;     /* * [7:4]QU command fifo real depth. */
        unsigned int quDataFifoDepth : 6;    /* * [13:8]QU data fifo real depth. */
        unsigned int lrb0FifoDepth : 5;      /* * [18:14]lrb0 fifo real depth. */
        unsigned int lrb1FifoDepth : 5;      /* * [23:19]lrb1 fifo real depth. */
        unsigned int lrb2FifoDepth : 5;      /* * [28:24]lrb2 fifo real depth. */
        unsigned int reserved : 3;           /* * [31:29] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_FIFO1_DEPTH_U;

/* **
 * Union name :    SMMC_F_MC_FIFO2_DEPTH
 * @brief               SMMC_F main cache FIFO depth
 * Description:
 */
typedef union tagUnSmmcFMcFifo2Depth {
    struct tagStSmmcFMcFifo2Depth {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 1;           /* * [31:31] */
        unsigned int quStoreBufferDepth : 9; /* * [30:22]QU store buffer real depth. */
        unsigned int rfbufCredit : 9;     /* * [21:13]refill buffer credit.The initial value is 0x100, indicate 256 64B
                                             credit. */
        unsigned int lrb3FifoDepth : 5;   /* * [12:8]lrb3 fifo real depth. */
        unsigned int quStoreBufferBp : 1; /* * [7:7]QU store buffer backpressure. */
        unsigned int quReturnFifoBp : 1;  /* * [6:6]QU return fifo backpressure. */
        unsigned int quReturnFifoDepth : 6; /* * [5:0]QU return fifo real depth. */
#else
        unsigned int quReturnFifoDepth : 6;  /* * [5:0]QU return fifo real depth. */
        unsigned int quReturnFifoBp : 1;     /* * [6:6]QU return fifo backpressure. */
        unsigned int quStoreBufferBp : 1;    /* * [7:7]QU store buffer backpressure. */
        unsigned int lrb3FifoDepth : 5;      /* * [12:8]lrb3 fifo real depth. */
        unsigned int rfbufCredit : 9; /* * [21:13]refill buffer credit.The initial value is 0x100, indicate 256 64B
                                         credit. */
        unsigned int quStoreBufferDepth : 9; /* * [30:22]QU store buffer real depth. */
        unsigned int reserved : 1;           /* * [31:31] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_FIFO2_DEPTH_U;

/* **
 * Union name :    SMMC_F_ERR_INJ
 * @brief
 * Description:
 */
typedef union tagUnSmmcFErrInj {
    struct tagStSmmcFErrInj {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 6;              /* * [31:26]reserved */
        unsigned int smmcSmxtfbUncrtErrInj : 1; /* * [25:25]smxt interface buffer ECC un-corrected err injection
                                             requestion;err injection start when posedge of this bit is detected; After
                                             Err injection start, err is inje cted when a memory read is issued to the
                                             memory. */
        unsigned int smmcSmxtfbCrtErrInj : 1;   /* * [24:24]smxt interface buffer ECC corrected err injection
                                             requestion;err injection start when posedge of this bit is detected; After
                                             Err injection start, err is injecte d when a memory read is issued to the
                                             memory. */
        unsigned int smmcStbUncrtErrInj : 1;    /* * [23:23]engine store buffer ECC un-corrected err injection
                                             requestion;err injection start when posedge of this bit is detected; After Err
                                             injection start, err is inject
                                             ed when a memory read is issued to the memory. */
        unsigned int smmcStbCrtErrInj : 1;   /* * [22:22]Engine store buffer ECC corrected err injection requestion;err
                                          injection start when posedge of this bit is detected; After Err injection start,
                                          err is injected when a memory read is issued to the memory. */
        unsigned int smmcVfaUncrtErrInj : 1; /* * [21:21]VFA table ECC un-corrected err injection requestion;err
                                          injection start when posedge of this bit is detected; After Err injection
                                          start, err is injected when a memory read is issued to the memory. */
        unsigned int smmcVfaCrtErrInj : 1;   /* * [20:20]VFA table ECC corrected err injection requestion;err injection
                                          start when posedge of this bit is detected; After Err injection start, err is
                                          injected when a mem ory read is issued to the memory. */
        unsigned int smmcRfBufUncrtErrInj : 1;  /* * [19:19]refill buffer ECC un-corrected err injection requestion;err
                                             injection start when posedge of this bit is detected; After Err injection
                                             start, err is injected whe n a memory read is issued to the memory. */
        unsigned int smmcRfBufCrtErrInj : 1;    /* * [18:18]refill buffer ECC corrected err injection requestion;err
                                              injection start when posedge of this bit is detected; After Err injection
                                              start, err is injected when a memory read is issued to the memory. */
        unsigned int smmcQuIntfUncrtErrInj : 1; /* * [17:17]QU interface buffer(include qu_data buffer, qu_lrn buffer
                                             and qu_store_data buffer) ECC un-corrected err injection requestion;err
                                             injection start when posedge o f this bit is detected; After Err injection
                                             start, err is injected when a memory read is issued to the memory.
                                              */
        unsigned int smmcQuIntfCrtErrInj : 1; /* * [16:16]QU interface buffer(include qu_data buffer, qu_lrn buffer and
                                           qu_store_data buffer) ECC corrected err injection requestion;err injection
                                           start when posedge of t his bit is detected; After Err injection start, err
                                           is injected when a memory read is issued to the memory.
                                            */
        unsigned int smmcMc3UncrtErrInj : 1; /* * [15:15]main cache bank3 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcMc3CrtErrInj : 1;   /* * [14:14]main cache bank3 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcMc2UncrtErrInj : 1; /* * [13:13]main cache bank2 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcMc2CrtErrInj : 1;   /* * [12:12]main cache bank2 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcMc1UncrtErrInj : 1; /* * [11:11]main cache bank1 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcMc1CrtErrInj : 1;   /* * [10:10]main cache bank1 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcMc0UncrtErrInj : 1; /* * [9:9]main cache bank0 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcMc0CrtErrInj : 1;   /* * [8:8]main cache bank0 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcVc3UncrtErrInj : 1; /* * [7:7]victim cache bank3 memory(include all memory in victim cache
                                          bank3) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcVc3CrtErrInj : 1; /* * [6:6]victim cache bank3 memory(include all memory in victim cache bank3)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
        unsigned int smmcVc2UncrtErrInj : 1; /* * [5:5]victim cache bank2 memory(include all memory in victim cache
                                          bank2) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcVc2CrtErrInj : 1; /* * [4:4]victim cache bank2 memory(include all memory in victim cache bank2)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
        unsigned int smmcVc1UncrtErrInj : 1; /* * [3:3]victim cache bank1 memory(include all memory in victim cache
                                          bank1) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcVc1CrtErrInj : 1; /* * [2:2]victim cache bank1 memory(include all memory in victim cache bank1)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
        unsigned int smmcVc0UncrtErrInj : 1; /* * [1:1]victim cache bank0 memory(include all memory in victim cache
                                          bank0) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcVc0CrtErrInj : 1; /* * [0:0]victim cache bank0 memory(include all memory in victim cache bank0)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
#else
        unsigned int smmcVc0CrtErrInj : 1; /* * [0:0]victim cache bank0 memory(include all memory in victim cache bank0)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
        unsigned int smmcVc0UncrtErrInj : 1; /* * [1:1]victim cache bank0 memory(include all memory in victim cache
                                          bank0) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcVc1CrtErrInj : 1; /* * [2:2]victim cache bank1 memory(include all memory in victim cache bank1)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
        unsigned int smmcVc1UncrtErrInj : 1; /* * [3:3]victim cache bank1 memory(include all memory in victim cache
                                          bank1) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcVc2CrtErrInj : 1; /* * [4:4]victim cache bank2 memory(include all memory in victim cache bank2)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
        unsigned int smmcVc2UncrtErrInj : 1; /* * [5:5]victim cache bank2 memory(include all memory in victim cache
                                          bank2) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcVc3CrtErrInj : 1; /* * [6:6]victim cache bank3 memory(include all memory in victim cache bank3)
                                        ECC corrected err injection requestion;err injection start when posedge of this
                                        bit is detec ted; After Err injection start, err is injected when a memory read
                                        is issued to the memory.
                                         */
        unsigned int smmcVc3UncrtErrInj : 1; /* * [7:7]victim cache bank3 memory(include all memory in victim cache
                                          bank3) ECC un-corrected err injection requestion;err injection start when
                                          posedge of this bit is de tected; After Err injection start, err is injected
                                          when a memory read is issued to the memory.
                                           */
        unsigned int smmcMc0CrtErrInj : 1;   /* * [8:8]main cache bank0 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcMc0UncrtErrInj : 1; /* * [9:9]main cache bank0 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcMc1CrtErrInj : 1;   /* * [10:10]main cache bank1 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcMc1UncrtErrInj : 1; /* * [11:11]main cache bank1 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcMc2CrtErrInj : 1;   /* * [12:12]main cache bank2 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcMc2UncrtErrInj : 1; /* * [13:13]main cache bank2 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcMc3CrtErrInj : 1;   /* * [14:14]main cache bank3 memory(include tag memory and data memory) ECC
                                          corrected err injection requestion;err injection start when posedge of this bit
                                          is detected; Aft er Err injection start, err is injected when a memory read is
                                          issued to the memory.
                                           */
        unsigned int smmcMc3UncrtErrInj : 1; /* * [15:15]main cache bank3 memory(include tag memory and data memory) ECC
                                          un-corrected err injection requestion;err injection start when posedge of this
                                          bit is detected; After Err injection start, err is injected when a memory read
                                          is issued to the memory.
                                           */
        unsigned int smmcQuIntfCrtErrInj : 1; /* * [16:16]QU interface buffer(include qu_data buffer, qu_lrn buffer and
                                           qu_store_data buffer) ECC corrected err injection requestion;err injection
                                           start when posedge of t his bit is detected; After Err injection start, err
                                           is injected when a memory read is issued to the memory.
                                            */
        unsigned int smmcQuIntfUncrtErrInj : 1; /* * [17:17]QU interface buffer(include qu_data buffer, qu_lrn buffer
                                             and qu_store_data buffer) ECC un-corrected err injection requestion;err
                                             injection start when posedge o f this bit is detected; After Err injection
                                             start, err is injected when a memory read is issued to the memory.
                                              */
        unsigned int smmcRfBufCrtErrInj : 1;    /* * [18:18]refill buffer ECC corrected err injection requestion;err
                                              injection start when posedge of this bit is detected; After Err injection
                                              start, err is injected when a memory read is issued to the memory. */
        unsigned int smmcRfBufUncrtErrInj : 1;  /* * [19:19]refill buffer ECC un-corrected err injection requestion;err
                                             injection start when posedge of this bit is detected; After Err injection
                                             start, err is injected whe n a memory read is issued to the memory. */
        unsigned int smmcVfaCrtErrInj : 1;    /* * [20:20]VFA table ECC corrected err injection requestion;err injection
                                           start when posedge of this bit is detected; After Err injection start, err is
                                           injected when a mem ory read is issued to the memory. */
        unsigned int smmcVfaUncrtErrInj : 1;  /* * [21:21]VFA table ECC un-corrected err injection requestion;err
                                           injection start when posedge of this bit is detected; After Err injection
                                           start, err is injected when a memory read is issued to the memory. */
        unsigned int smmcStbCrtErrInj : 1;    /* * [22:22]Engine store buffer ECC corrected err injection requestion;err
                                           injection start when posedge of this bit is detected; After Err injection start,
                                           err is injected when a memory read is issued to the memory. */
        unsigned int smmcStbUncrtErrInj : 1;  /* * [23:23]engine store buffer ECC un-corrected err injection
                                           requestion;err injection start when posedge of this bit is detected; After Err
                                           injection start, err is inject
                                           ed when a memory read is issued to the memory. */
        unsigned int smmcSmxtfbCrtErrInj : 1; /* * [24:24]smxt interface buffer ECC corrected err injection
                                           requestion;err injection start when posedge of this bit is detected; After
                                           Err injection start, err is injecte d when a memory read is issued to the
                                           memory. */
        unsigned int smmcSmxtfbUncrtErrInj : 1; /* * [25:25]smxt interface buffer ECC un-corrected err injection
                                             requestion;err injection start when posedge of this bit is detected; After
                                             Err injection start, err is inje cted when a memory read is issued to the
                                             memory. */
        unsigned int reserved : 6;              /* * [31:26]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_ERR_INJ_U;

/* **
 * Union name :    SMMC_F_GPA_TRANS_ERR
 * @brief
 * Description:
 */
typedef union tagUnSmmcFGpaTransErr {
    struct tagStSmmcFGpaTransErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int sticky : 30; /* * [31:2]captures error state of BAT or CLA GPA.[31:21]:reserved;[20]:error type.
                              1:memory index error; 0:GPA is invalid;[19:10]:VF-ID;[9:6]:tag_type;[5:4]:current CLA l
                              ev:      2'b00:0 level CLA;      2'b01:1 level CLA;      2'B10:2 level CLA;[3:2]:total CLA
                              lev:      2'b00:0 level;      2'b01:1 level;      2'b10:2 level;
                               */
        unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int errorBit : 1;      /* * [0:0]0:no error founded1:error founded */
#else
        unsigned int errorBit : 1;              /* * [0:0]0:no error founded1:error founded */
        unsigned int multiErrorBit : 1;         /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */
        unsigned int sticky : 30; /* * [31:2]captures error state of BAT or CLA GPA.[31:21]:reserved;[20]:error type.
                              1:memory index error; 0:GPA is invalid;[19:10]:VF-ID;[9:6]:tag_type;[5:4]:current CLA l
                              ev:      2'b00:0 level CLA;      2'b01:1 level CLA;      2'B10:2 level CLA;[3:2]:total CLA
                              lev:      2'b00:0 level;      2'b01:1 level;      2'b10:2 level;
                               */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_GPA_TRANS_ERR_U;

/* **
 * Union name :    SMMC_F_QU_INTF_CNT_CFG
 * @brief
 * Description:
 */
typedef union tagUnSmmcFQuIntfCntCfg {
    struct tagStSmmcFQuIntfCntCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int
            smmcFQuIntfRxCntCfg : 16; /* * [31:16]qu_interface API received counter configuration, API received counter
                                  is used to count for API request that sent from QU to
                                  SMMC_F:qu_intf_rx_cnt和qu_rx_flit_ctp
                                  共用该寄存器的配置参数。qu_intf_rx_cnt要计数的API类型，qu_rx_flit_ctp要抓的数据类型，都由该寄存器的bit【30:16】决定。[31]:counter
                                  enable.      1'b0: disable counter;     1'b1: enable coutner;[30]:VF_ ID configuration
                                  enable. If this bit is valid, counter will count for API by the VF_ID configured by
                                  CSR.[29]:TAG_TYPE configuration enable. If this bit is vali d, counter will count for
                                  API by the tag_type configured by CSR.[28]:OPCODE configuration enable. If this bit is
                                  valid, counter will count for API by the opcode configured by CSR.[27:19]:VF_ID. If
                                  bit[30] is valid, counter will count for API by this
                                  field.(NOTE:当该参数用来配置qu_intf_rx_cnt时，配的是映射后的VF_ID.当该参数用来配置qu_rx_flit_ct
                                  p时，配的是映射之前的VF_ID.)[18:17]:TAG_TYPE. If bit[29] is valid, counter will count
                                  for API by this field.   2'b00: flow table parent context;   2'b01: RDMA parent cont
                                  ext;   2'b10: child context;   2'b11: reserved;[16]:OPCODE. If bit[28] is valid,
                                  counter will count for API by this field.   1'b0: load;   1'b1: store;Note:bit[ 30:28]
                                  could be configured to enable or disable independently. If bit[30:28] are all valid,
                                  counter will count for API by VF_ID and TAG_TYPE and OPCODE at the s ame time. If none
                                  of bit[30:28] is valid, counter will count for any API received.
                                   */
        unsigned int
            smmcFQuIntfTxCntCfg : 16; /* * [15:0]qu_interface API transmited counter configuration, API transmit
                                  counter is used to count for API response that sent from SMMC_F to
                                  QU:qu_intf_tx_cnt和qu_tx_flit_
                                  ctp共用该寄存器的配置参数。qu_intf_tx_cnt要计数的API类型，qu_tx_flit_ctp要抓的数据类型，都由该寄存器的bit【14:0】决定。[15]:counter
                                  enable.      1'b0: disable counter;     1'b1: enable coutner;[14]:V F_ID
                                  configuration enable. If this bit is valid, counter will count for API by the
                                  VF_ID configured by CSR.[13]:TAG_TYPE configuration enable. If this bit is va
                                  lid, counter will count for API by the tag_type configured by CSR.[12]:OPCODE
                                  configuration enable. If this bit is valid, counter will count for API by the
                                  opco de configured by CSR.[11:3]:VF_ID. If bit[14] is valid, counter will
                                  count for API by this field.(NOTE:该参数配的是映射后的VF_ID.)[2:1]:TAG_TYPE.
                                  If bit[13] is valid, cou nter will count for API by this field.   2'b00: flow
                                  table parent context;   2'b01: RDMA parent context;   2'b10: child context;
                                  2'b11: reserved;[0]:OPCODE. I f bit[12] is valid, counter will count for API
                                  by this field.   1'b0: load;   1'b1: store;Note:bit[14:12] could be
                                  configured to enable or disable independently . If bit[14:12] are all valid,
                                  counter will count for API by VF_ID and TAG_TYPE and OPCODE at the same time.
                                  If none of bit[14:12] is valid, counter will count for any API sent. */
#else
        unsigned int
            smmcFQuIntfTxCntCfg : 16; /* * [15:0]qu_interface API transmited counter configuration, API transmit
                                  counter is used to count for API response that sent from SMMC_F to
                                  QU:qu_intf_tx_cnt和qu_tx_flit_
                                  ctp共用该寄存器的配置参数。qu_intf_tx_cnt要计数的API类型，qu_tx_flit_ctp要抓的数据类型，都由该寄存器的bit【14:0】决定。[15]:counter
                                  enable.      1'b0: disable counter;     1'b1: enable coutner;[14]:V F_ID
                                  configuration enable. If this bit is valid, counter will count for API by the
                                  VF_ID configured by CSR.[13]:TAG_TYPE configuration enable. If this bit is va
                                  lid, counter will count for API by the tag_type configured by CSR.[12]:OPCODE
                                  configuration enable. If this bit is valid, counter will count for API by the
                                  opco de configured by CSR.[11:3]:VF_ID. If bit[14] is valid, counter will
                                  count for API by this field.(NOTE:该参数配的是映射后的VF_ID.)[2:1]:TAG_TYPE.
                                  If bit[13] is valid, cou nter will count for API by this field.   2'b00: flow
                                  table parent context;   2'b01: RDMA parent context;   2'b10: child context;
                                  2'b11: reserved;[0]:OPCODE. I f bit[12] is valid, counter will count for API
                                  by this field.   1'b0: load;   1'b1: store;Note:bit[14:12] could be
                                  configured to enable or disable independently . If bit[14:12] are all valid,
                                  counter will count for API by VF_ID and TAG_TYPE and OPCODE at the same time.
                                  If none of bit[14:12] is valid, counter will count for any API sent. */
        unsigned int
            smmcFQuIntfRxCntCfg : 16; /* * [31:16]qu_interface API received counter configuration, API received counter
                                  is used to count for API request that sent from QU to
                                  SMMC_F:qu_intf_rx_cnt和qu_rx_flit_ctp
                                  共用该寄存器的配置参数。qu_intf_rx_cnt要计数的API类型，qu_rx_flit_ctp要抓的数据类型，都由该寄存器的bit【30:16】决定。[31]:counter
                                  enable.      1'b0: disable counter;     1'b1: enable coutner;[30]:VF_ ID configuration
                                  enable. If this bit is valid, counter will count for API by the VF_ID configured by
                                  CSR.[29]:TAG_TYPE configuration enable. If this bit is vali d, counter will count for
                                  API by the tag_type configured by CSR.[28]:OPCODE configuration enable. If this bit is
                                  valid, counter will count for API by the opcode configured by CSR.[27:19]:VF_ID. If
                                  bit[30] is valid, counter will count for API by this
                                  field.(NOTE:当该参数用来配置qu_intf_rx_cnt时，配的是映射后的VF_ID.当该参数用来配置qu_rx_flit_ct
                                  p时，配的是映射之前的VF_ID.)[18:17]:TAG_TYPE. If bit[29] is valid, counter will count
                                  for API by this field.   2'b00: flow table parent context;   2'b01: RDMA parent cont
                                  ext;   2'b10: child context;   2'b11: reserved;[16]:OPCODE. If bit[28] is valid,
                                  counter will count for API by this field.   1'b0: load;   1'b1: store;Note:bit[ 30:28]
                                  could be configured to enable or disable independently. If bit[30:28] are all valid,
                                  counter will count for API by VF_ID and TAG_TYPE and OPCODE at the s ame time. If none
                                  of bit[30:28] is valid, counter will count for any API received.
                                   */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_QU_INTF_CNT_CFG_U;

/* **
 * Union name :    SMMC_F_QU_INTF_RX_CNT
 * @brief
 * Description:
 */
typedef union tagUnSmmcFQuIntfRxCnt {
    struct tagStSmmcFQuIntfRxCnt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFQuIntfRxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the
                                               configuration. */
#else
        unsigned int smmcFQuIntfRxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the
                                               configuration. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_QU_INTF_RX_CNT_U;

/* **
 * Union name :    SMMC_F_QU_INTF_TX_CNT
 * @brief
 * Description:
 */
typedef union tagUnSmmcFQuIntfTxCnt {
    struct tagStSmmcFQuIntfTxCnt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFQuIntfTxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the
                                               configuration. */
#else
        unsigned int smmcFQuIntfTxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the
                                               configuration. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_QU_INTF_TX_CNT_U;

/* **
 * Union name :    SMMC_F_MC_CFG2
 * @brief
 * Description:
 */
typedef union tagUnSmmcFMcCfg2 {
    struct tagStSmmcFMcCfg2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 21;          /* * [31:11] */
        unsigned int mcRefillTimeoutEnb : 1; /* * [10:10]enable SMMC to monitor and check if a refill request to CPI is
                                                timeout. */
        unsigned int smfCommonMemPowerMode : 6; /* * [9:4]memory power mode control, this signal is used to control
                                                 * memory in SMXR,and SMMC(except tag memory and data memory in main
                                                 * cache and victim cache)
                                                 */
        unsigned int
            smmcFRfErrCtpClr : 1; /* * [3:3]clear the refill error information and restart to capture next refill error
                               information. The refill error information could be read via CSR indirect access.Note
                               :该信号是用来清除refill error捕抓的信息,并且重新开始捕抓下一个refill
                               error的信息的。正常的流程应该是，refill
                               error报中断后，软件通过CSR间接读写接口去读取捕抓的错误信息（捕抓信息的bit0等于时表示捕抓的信息有效），读取分析完后再通过该信号去清除捕抓的信息。该信号是上升沿触发清零
                               操作，如果多次清零，需要先把该信号写成零，再写成一，这样SMMC会产生一个上升沿脉冲信号，并用该脉冲信号清零。
                             */
        unsigned int smmcFRttCntEnb : 1;   /* * [2:2]SMMC_F support to record the longest/shortest latency of refilling
                                        from CPI, or record the longest/shortest operating latency in SMMC_F.If this
                                        signal is enable , SMMC_F issue a counter to record the latency, and capture the
                                        latency in two register:rtt_ctp_short and rtt_ctp_long. these two register can be
                                        read by SW via CSR indirect access. */
        unsigned int smmcFRttCntType : 1;  /* * [1:1]SW can configure this signal to indicate SMMC_F which type of
                                            * latency to record:0:record API operating latency in SMMC_F.1:record refill
                                            * latency from CPI.
                                            */
        unsigned int smmcFRscCntMixEn : 1; /* * [0:0]If rsc_cnt_mix_en=1, SQ WQE and RQ WQE and other data structures
                                        share the same virtual cache.SMMC doesn't differentiate WQE type (SQ WQE and RQ
                                        WQE) in this ca se, SMMC just maintains one resource counter.If
                                        rsc_cnt_mix_en=0, SQ WQE uses a separate virtual cache (only SQ WQE in this
                                        virtual cache). RQ WQE uses another separate virtual cache (only RQ WQE in this
                                        virtual cache).SQ resource counter and RQ resource counter are counted
                                        independently.
                                         */
#else
        unsigned int smmcFRscCntMixEn : 1;  /* * [0:0]If rsc_cnt_mix_en=1, SQ WQE and RQ WQE and other data structures
                                         share the same virtual cache.SMMC doesn't differentiate WQE type (SQ WQE and RQ
                                         WQE) in this ca se, SMMC just maintains one resource counter.If
                                         rsc_cnt_mix_en=0, SQ WQE uses a separate virtual cache (only SQ WQE in this
                                         virtual cache). RQ WQE uses another separate virtual cache (only RQ WQE in this
                                         virtual cache).SQ resource counter and RQ resource counter are counted
                                         independently.
                                          */
        unsigned int smmcFRttCntType : 1;   /* * [1:1]SW can configure this signal to indicate SMMC_F which type of
                                             * latency to record:0:record API operating latency in SMMC_F.1:record refill
                                             * latency from CPI.
                                             */
        unsigned int smmcFRttCntEnb : 1;    /* * [2:2]SMMC_F support to record the longest/shortest latency of refilling
                                         from CPI, or record the longest/shortest operating latency in SMMC_F.If this
                                         signal is enable , SMMC_F issue a counter to record the latency, and capture the
                                         latency in two register:rtt_ctp_short and rtt_ctp_long. these two register can be
                                         read by SW via CSR indirect access. */
        unsigned int
            smmcFRfErrCtpClr : 1; /* * [3:3]clear the refill error information and restart to capture next refill error
                               information. The refill error information could be read via CSR indirect access.Note
                               :该信号是用来清除refill error捕抓的信息,并且重新开始捕抓下一个refill
                               error的信息的。正常的流程应该是，refill
                               error报中断后，软件通过CSR间接读写接口去读取捕抓的错误信息（捕抓信息的bit0等于时表示捕抓的信息有效），读取分析完后再通过该信号去清除捕抓的信息。该信号是上升沿触发清零
                               操作，如果多次清零，需要先把该信号写成零，再写成一，这样SMMC会产生一个上升沿脉冲信号，并用该脉冲信号清零。
                             */
        unsigned int smfCommonMemPowerMode : 6; /* * [9:4]memory power mode control, this signal is used to control
                                                 * memory in SMXR,and SMMC(except tag memory and data memory in main
                                                 * cache and victim cache)
                                                 */
        unsigned int mcRefillTimeoutEnb : 1; /* * [10:10]enable SMMC to monitor and check if a refill request to CPI is
                                                timeout. */
        unsigned int reserved : 21;          /* * [31:11] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_F_MC_CFG2_U;


/* **
 * Union name :    SMMC_L_VERSION
 * @brief               reserved for ECO
 * Description:
 */
typedef union tagUnSmmcLVersion {
    struct tagStSmmcLVersion {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcLVersion : 32; /* * [31:0]reserved for ECO */
#else
        unsigned int smmcLVersion : 32;      /* * [31:0]reserved for ECO */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_VERSION_U;

/* **
 * Union name :    SMMC_L_CFG
 * @brief               SMMC_L configure register
 * Description:
 */
typedef union tagUnSmmcLCfg {
    struct tagStSmmcLCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int memRet1nDiv2 : 1;   /* * [31:31]control of memory pin RET1N */
        unsigned int spRamTmodDiv2 : 7;  /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                          * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                          */
        unsigned int memRet1n : 1;       /* * [23:23]control of memory pin RET1N */
        unsigned int spRamTmod : 7;      /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                          * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                          */
        unsigned int reserved : 13;      /* * [15:3]reserved */
        unsigned int memIniEn : 1;       /* * [2:2]Enable to initialize internal memory1: enable;0: disable */
        unsigned int smmcLEccChk : 1;    /* * [1:1]ECC error check enable */
        unsigned int smmcLParityChk : 1; /* * [0:0]reserved */
#else
        unsigned int smmcLParityChk : 1;     /* * [0:0]reserved */
        unsigned int smmcLEccChk : 1;        /* * [1:1]ECC error check enable */
        unsigned int memIniEn : 1;           /* * [2:2]Enable to initialize internal memory1: enable;0: disable */
        unsigned int reserved : 13;          /* * [15:3]reserved */
        unsigned int spRamTmod : 7;     /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                         * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                         */
        unsigned int memRet1n : 1;      /* * [23:23]control of memory pin RET1N */
        unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =<
                                         * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0
                                         */
        unsigned int memRet1nDiv2 : 1;  /* * [31:31]control of memory pin RET1N */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CFG_U;

/* **
 * Union name :    SMMC_L_STAT
 * @brief               SMMC_L status register
 * Description:
 */
typedef union tagUnSmmcLStat {
    struct tagStSmmcLStat {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 31;  /* * [31:1] */
        unsigned int memIniDone : 1; /* * [0:0]Indicate whether memory initialization done or not1: Done0: not complete
                                      */
#else
        unsigned int memIniDone : 1; /* * [0:0]Indicate whether memory initialization done or not1: Done0: not complete
                                      */
        unsigned int reserved : 31;  /* * [31:1] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_STAT_U;

/* **
 * Union name :    SMMC_L_INT_VECTOR
 * @brief               SMMC_L interrupt vector register
 * Description:
 */
typedef union tagUnSmmcLIntVector {
    struct tagStSmmcLIntVector {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 3; /* * [31:29]reserved */
        unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes
                                    * 0 to clear.
                                    */
        unsigned int enable : 1;   /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                    * register0:interrupt disable1:interrupt enable
                                    */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
#else
        unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index.  Software should guarantee
                                   that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]},
                                   dest_ pf[16] is for the uP; */
        unsigned int reserved1 : 3;    /* * [26:24]reserved */
        unsigned int enable : 1;       /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this
                                        * register0:interrupt disable1:interrupt enable
                                        */
        unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes
                                    * 0 to clear.
                                    */
        unsigned int reserved0 : 3;     /* * [31:29]reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_INT_VECTOR_U;

/* **
 * Union name :    SMMC_L_INT
 * @brief               SMMC_L interrupt register
 * Description:
 */
typedef union tagUnSmmcLInt {
    struct tagStSmmcLInt {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 15;     /* * [15:1] */
        unsigned int intData : 1;       /* * [0:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
#else
        unsigned int intData : 1;       /* * [0:0]interrupt masked field,it is the collection of the error bits from the
                                         * corresponding error registers on the sheet
                                         */
        unsigned int reserved : 15;     /* * [15:1] */
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_INT_U;

/* **
 * Union name :    SMMC_L_INT_MASK
 * @brief               SMMC_L interrupt mask register
 * Description:
 */
typedef union tagUnSmmcLIntMask {
    struct tagStSmmcLIntMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                         * of CSR modules) asked for the interrupt
                                         */
        unsigned int reserved : 15;     /* * [15:1] */
        unsigned int errMask : 1; /* * [0:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
#else
        unsigned int errMask : 1; /* * [0:0]error register mask flag, it is the same mapping from the interrupt register
                                   * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable
                                   */
        unsigned int reserved : 15;       /* * [15:1] */
        unsigned int programCsrId : 16;   /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group
                                           * of CSR modules) asked for the interrupt
                                           */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_INT_MASK_U;

/* **
 * Union name :    SMMC_L_MEM_ERR
 * @brief               SMMC_L MEM error register
 * Description:
 */
typedef union tagUnSmmcLMemErr {
    struct tagStSmmcLMemErr {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 28;        /* * [31:4]reserved. */
        unsigned int mainMem1bEccMerr : 1; /* * [3:3] */
        unsigned int mainMem1bEccErr : 1;  /* * [2:2]main memory 1 bit ECC error */
        unsigned int mainMem2bEccMerr : 1; /* * [1:1]multi times of main memory 2 bit ECC error */
        unsigned int mainMem2bEccErr : 1;  /* * [0:0]main memory 2 bit ECC error */
#else
        unsigned int mainMem2bEccErr : 1; /* * [0:0]main memory 2 bit ECC error */
        unsigned int mainMem2bEccMerr : 1;    /* * [1:1]multi times of main memory 2 bit ECC error */
        unsigned int mainMem1bEccErr : 1;     /* * [2:2]main memory 1 bit ECC error */
        unsigned int mainMem1bEccMerr : 1;    /* * [3:3] */
        unsigned int reserved : 28;           /* * [31:4]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_MEM_ERR_U;

/* **
 * Union name :    SMMC_L_MEM_ERR_MASK
 * @brief               SMMC_L MEM error mask register
 * Description:
 */
typedef union tagUnSmmcLMemErrMask {
    struct tagStSmmcLMemErrMask {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 30;           /* * [31:2]reserved. */
        unsigned int mainMem1bEccErrMask : 1; /* * [1:1]main memory 1 bit ECC error mask */
        unsigned int mainMem2bEccErrMask : 1; /* * [0:0]main memory 2 bit ECC error mask */
#else
        unsigned int mainMem2bEccErrMask : 1; /* * [0:0]main memory 2 bit ECC error mask */
        unsigned int mainMem1bEccErrMask : 1; /* * [1:1]main memory 1 bit ECC error mask */
        unsigned int reserved : 30;           /* * [31:2]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_MEM_ERR_MASK_U;

/* **
 * Union name :    SMMC_L_MEM_ERR_INFO
 * @brief               SMMC_L MEM error info register
 * Description:
 */
typedef union tagUnSmmcLMemErrInfo {
    struct tagStSmmcLMemErrInfo {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved0 : 14;     /* * [31:18]reserved. */
        unsigned int memErrInfoType : 2; /* * [17:16]Indicate which error's info is captured:00: main memory has 1 bit
                                          * ECC error;01: main memory has 2 bit ECC error;10~11: reserved
                                          */
        unsigned int reserved1 : 1;      /* * [15:15]reserved bit */
        unsigned int memErrIndex : 15;   /* * [14:0]Indicate the address of entry meeting error.For main memory,
                                          * index[14:0] is usage for 32 K entries of 32 byte.
                                          */
#else
        unsigned int memErrIndex : 15;        /* * [14:0]Indicate the address of entry meeting error.For main memory,
                                               * index[14:0] is usage for 32 K entries of 32 byte.
                                               */
        unsigned int reserved1 : 1;           /* * [15:15]reserved bit */
        unsigned int memErrInfoType : 2; /* * [17:16]Indicate which error's info is captured:00: main memory has 1 bit
                                          * ECC error;01: main memory has 2 bit ECC error;10~11: reserved
                                          */
        unsigned int reserved0 : 14;     /* * [31:18]reserved. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_MEM_ERR_INFO_U;

/* **
 * Union name :    SMMC_L_INDRECT_CTRL
 * @brief               indirect access address registers
 * Description:
 */
typedef union tagUnSmmcLIndrectCtrl {
    struct tagStSmmcLIndrectCtrl {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcLIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
        unsigned int smmcLIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smmcLIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smmcLIndirTab : 4;  /* * [27:24]It specifies memory group or table. 4'h0: main memory;4'h1: ECC
                                      memory.ECC memory only can rightly read or write in debug mode without normal
                                      datapath stream.4' h2: loopback CAM request info and link info.It only support to
                                      read and not to write;4'h3: slot ring.It only support to read and not to
                                      write;4'h4: bank queue i nfo.It only support to read and not to write;4'h5:
                                      reserved;4'h6: reserved4'h7~4'hf: reserved
                                       */
        unsigned int
            smmcLIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one
                             group or internal address of the table.(1) Main memory:Total size is 1M byte and one e ntry
                             is 32 byte.Index[17:0] is usage for access main memory.Index[17:3] address to one entry,
                             and index[2:0] address to one 4 byte in one entry.index[2:0]000: e ntry[255:224];001:
                             entry[223:192];010: entry[191:160];011: entry[159:128];100: entry[127:96];101:
                             entry[95:64];110: entry[63:32];111: entry[31:0];(2) ECC memory One 10 bit ECC protects one
                             entry of main memory.16 ECC of 10 bits is grouped as one entry of ECC memory and total
                             number of entries is 2 K. Index[14:0] address one entry of 10 bit ECC. One entry
                             is{22'd0,EEC[9:0]};(3) Loopback CAM and Request info and Link infoThese are addressed by
                             request ID.Total number of request ID is 16. Index[3:0] address one entry of one request
                             ID. One entry's datastructre:entry[31:24]: loopback CAM[7:0];entry[23:21]: reserved 3
                             bit;entry[20:4]: req uest info[16:0];entry[3:0]: link info[3:0]; (4) Slot ringSlot ring
                             only has 8 bits, index is unused.(5) Bank queue list info;Bank queue list info is addressed
                             b y bank ID, and total number of bank in SMMC_L is 16 banks. Once CSR can access 2 bank
                             queue list infos as an entry. Its datastructure isEntry[31:26]: reserved 6
                              bits;Entry[25:16]: bank queue list info[9:0]Entry[15:10]: reserved 6 bits;Entry[9:0]: bank
                             queue list info[9:0]Index[2:0] address one entry;000: bank 0 and ban k 1's list info001:
                             bank 2 and bank 3's list info010: bank 4 and bank 5's list info011: bank 6 and bank 7's
                             list info100: bank 8 and bank 9's list info101: bank 10 and bank 11's list info110: bank 12
                             and bank 13's list info111: bank 14 and bank 15's list info(6) reserved
                              */
#else
        unsigned int
            smmcLIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one
                             group or internal address of the table.(1) Main memory:Total size is 1M byte and one e ntry
                             is 32 byte.Index[17:0] is usage for access main memory.Index[17:3] address to one entry,
                             and index[2:0] address to one 4 byte in one entry.index[2:0]000: e ntry[255:224];001:
                             entry[223:192];010: entry[191:160];011: entry[159:128];100: entry[127:96];101:
                             entry[95:64];110: entry[63:32];111: entry[31:0];(2) ECC memory One 10 bit ECC protects one
                             entry of main memory.16 ECC of 10 bits is grouped as one entry of ECC memory and total
                             number of entries is 2 K. Index[14:0] address one entry of 10 bit ECC. One entry
                             is{22'd0,EEC[9:0]};(3) Loopback CAM and Request info and Link infoThese are addressed by
                             request ID.Total number of request ID is 16. Index[3:0] address one entry of one request
                             ID. One entry's datastructre:entry[31:24]: loopback CAM[7:0];entry[23:21]: reserved 3
                             bit;entry[20:4]: req uest info[16:0];entry[3:0]: link info[3:0]; (4) Slot ringSlot ring
                             only has 8 bits, index is unused.(5) Bank queue list info;Bank queue list info is addressed
                             b y bank ID, and total number of bank in SMMC_L is 16 banks. Once CSR can access 2 bank
                             queue list infos as an entry. Its datastructure isEntry[31:26]: reserved 6
                              bits;Entry[25:16]: bank queue list info[9:0]Entry[15:10]: reserved 6 bits;Entry[9:0]: bank
                             queue list info[9:0]Index[2:0] address one entry;000: bank 0 and ban k 1's list info001:
                             bank 2 and bank 3's list info010: bank 4 and bank 5's list info011: bank 6 and bank 7's
                             list info100: bank 8 and bank 9's list info101: bank 10 and bank 11's list info110: bank 12
                             and bank 13's list info111: bank 14 and bank 15's list info(6) reserved
                              */
        unsigned int smmcLIndirTab : 4;  /* * [27:24]It specifies memory group or table. 4'h0: main memory;4'h1: ECC
                                      memory.ECC memory only can rightly read or write in debug mode without normal
                                      datapath stream.4' h2: loopback CAM request info and link info.It only support to
                                      read and not to write;4'h3: slot ring.It only support to read and not to
                                      write;4'h4: bank queue i nfo.It only support to read and not to write;4'h5:
                                      reserved;4'h6: reserved4'h7~4'hf: reserved
                                       */
        unsigned int smmcLIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access
                                          * done;2’b01: indirect access timeout;Others: reserved.
                                          */
        unsigned int smmcLIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */
        unsigned int smmcLIndirVld : 1;  /* * [31:31]It specifies the indirect access validation:1’b0: indirect access
                                      invalid, including operation done and timeout (initial value or logic clear);1’b1:
                                      indirect ac cess valid (software set). */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_INDRECT_CTRL_U;

/* **
 * Union name :    SMMC_L_INDRECT_TIMEOUT
 * @brief               memory access timeout configure
 * Description:
 */
typedef union tagUnSmmcLIndrectTimeout {
    struct tagStSmmcLIndrectTimeout {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcLIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#else
        unsigned int smmcLIndirTimeout : 32; /* * [31:0]memory access timeout configure */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_INDRECT_TIMEOUT_U;

/* **
 * Union name :    SMMC_L_INDRECT_DATA
 * @brief               indirect access data registers
 * Description:
 */
typedef union tagUnSmmcLIndrectData {
    struct tagStSmmcLIndrectData {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write:
                                       Software write data to these registes and then enable indirect access, logic will
                                       send these data to target.When operation read:  Logic write data to these
                                       registers and refresh xxx_indir_stat, software will get these data from target.
                                       */
#else
        unsigned int smmcFIndirData : 32;    /* * [31:0]It specifies the indirect access data:When operation write:
                                          Software write data to these registes and then enable indirect access, logic will
                                          send these data to target.When operation read:  Logic write data to these
                                          registers and refresh xxx_indir_stat, software will get these data from target.
                                          */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_INDRECT_DATA_U;

/* **
 * Union name :    SMMC_L_CNT_CFG
 * @brief               SMMC_L counter configure register
 * Description:
 */
typedef union tagUnSmmcLCntCfg {
    struct tagStSmmcLCntCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 12;   /* * [31:20] */
        unsigned int cnt3Sel : 2;     /* * [19:18]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int cnt2Sel : 2;     /* * [17:16]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int cnt1Sel : 2;     /* * [15:14]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int cnt0Sel : 2;     /* * [13:12]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int cnt3MatchEn : 2; /* * [11:10]00: count for all types01: reserved 10: counter for matched bank
                                       * ID;11: reserved;
                                       */
        unsigned int cnt2MatchEn : 2; /* * [9:8]00: count for all types01: reserved 10: counter for matched bank ID;11:
                                       * reserved;
                                       */
        unsigned int cnt1MatchEn : 2; /* * [7:6]00: count for all types01: reserved 10: counter for matched bank ID;11:
                                       * reserved;
                                       */
        unsigned int cnt0MatchEn : 2; /* * [5:4]00: count for all types01: reserved 10: counter for matched bank ID;11:
                                       * reserved;
                                       */
        unsigned int cnt3Enable : 1;  /* * [3:3]1: counter3 is enabled            0: counter3 is disabled */
        unsigned int cnt2Enable : 1;  /* * [2:2]1: counter2 is enabled            0: counter2 is disabled */
        unsigned int cnt1Enable : 1;  /* * [1:1]1: counter1 is enabled            0: counter1 is disabled */
        unsigned int cnt0Enable : 1;  /* * [0:0]1: counter0 is enabled            0: counter0 is disabled */
#else
        unsigned int cnt0Enable : 1;         /* * [0:0]1: counter0 is enabled            0: counter0 is disabled */
        unsigned int cnt1Enable : 1;         /* * [1:1]1: counter1 is enabled            0: counter1 is disabled */
        unsigned int cnt2Enable : 1;         /* * [2:2]1: counter2 is enabled            0: counter2 is disabled */
        unsigned int cnt3Enable : 1;         /* * [3:3]1: counter3 is enabled            0: counter3 is disabled */
        unsigned int cnt0MatchEn : 2; /* * [5:4]00: count for all types01: reserved 10: counter for matched bank ID;11:
                                       * reserved;
                                       */
        unsigned int cnt1MatchEn : 2; /* * [7:6]00: count for all types01: reserved 10: counter for matched bank ID;11:
                                       * reserved;
                                       */
        unsigned int cnt2MatchEn : 2; /* * [9:8]00: count for all types01: reserved 10: counter for matched bank ID;11:
                                       * reserved;
                                       */
        unsigned int cnt3MatchEn : 2; /* * [11:10]00: count for all types01: reserved 10: counter for matched bank
                                       * ID;11: reserved;
                                       */
        unsigned int cnt0Sel : 2;     /* * [13:12]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int cnt1Sel : 2;     /* * [15:14]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int cnt2Sel : 2;     /* * [17:16]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int cnt3Sel : 2;     /* * [19:18]00: load reqeust;01: store request;10: partial store request;11: load
                                         response; */
        unsigned int reserved : 12;   /* * [31:20] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CNT_CFG_U;

/* **
 * Union name :    SMMC_L_CNT_MATCH_BANK
 * @brief               SMMC_L counter configure register for matching instance ID
 * Description:
 */
typedef union tagUnSmmcLCntMatchBank {
    struct tagStSmmcLCntMatchBank {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 16;     /* * [31:16] */
        unsigned int cnt3MatchBank : 4; /* * [15:12]Bank ID for counter 3 */
        unsigned int cnt2MatchBank : 4; /* * [11:8]Bank ID for counter 2 */
        unsigned int cnt1MatchBank : 4; /* * [7:4]Bank ID for counter 1 */
        unsigned int cnt0MatchBank : 4; /* * [3:0]Bank ID for counter 0 */
#else
        unsigned int cnt0MatchBank : 4; /* * [3:0]Bank ID for counter 0 */
        unsigned int cnt1MatchBank : 4; /* * [7:4]Bank ID for counter 1 */
        unsigned int cnt2MatchBank : 4; /* * [11:8]Bank ID for counter 2 */
        unsigned int cnt3MatchBank : 4; /* * [15:12]Bank ID for counter 3 */
        unsigned int reserved : 16;     /* * [31:16] */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CNT_MATCH_BANK_U;

/* **
 * Union name :    SMMC_L_CNT_MATCH_INSTANCE
 * @brief               SMMC_L counter configure register for matching instance ID
 * Description:
 */
typedef union tagUnSmmcLCntMatchInstance {
    struct tagStSmmcLCntMatchInstance {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 12; /* * [31:20]SMMC_L does not see instance ID, so that this configuration is not used
                                     */
        unsigned int cnt3MatchInst : 5; /* * [19:15]Reserved */
        unsigned int cnt2MatchInst : 5; /* * [14:10]Reserved */
        unsigned int cnt1MatchInst : 5; /* * [9:5]Reserved */
        unsigned int cnt0MatchInst : 5; /* * [4:0]Reserved */
#else
        unsigned int cnt0MatchInst : 5; /* * [4:0]Reserved */
        unsigned int cnt1MatchInst : 5; /* * [9:5]Reserved */
        unsigned int cnt2MatchInst : 5; /* * [14:10]Reserved */
        unsigned int cnt3MatchInst : 5; /* * [19:15]Reserved */
        unsigned int reserved : 12;  /* * [31:20]SMMC_L does not see instance ID, so that this configuration is not used
                                      */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CNT_MATCH_INSTANCE_U;

/* **
 * Union name :    SMMC_L_CNT0
 * @brief               SMMC_L counter 0 register
 * Description:
 */
typedef union tagUnSmmcLCnt0 {
    struct tagStSmmcLCnt0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcLCnt0 : 32; /* * [31:0]Couner 0 accroding to counter configure register. */
#else
        unsigned int smmcLCnt0 : 32; /* * [31:0]Couner 0 accroding to counter configure register. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CNT0_U;

/* **
 * Union name :    SMMC_L_CNT1
 * @brief               SMMC_L counter 1 register
 * Description:
 */
typedef union tagUnSmmcLCnt1 {
    struct tagStSmmcLCnt1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcLCnt1 : 32; /* * [31:0]Couner 1 accroding to counter configure register. */
#else
        unsigned int smmcLCnt1 : 32; /* * [31:0]Couner 1 accroding to counter configure register. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CNT1_U;

/* **
 * Union name :    SMMC_L_CNT2
 * @brief               SMMC_L counter 2 register
 * Description:
 */
typedef union tagUnSmmcLCnt2 {
    struct tagStSmmcLCnt2 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcLCnt2 : 32; /* * [31:0]Couner 2 accroding to counter configure register. */
#else
        unsigned int smmcLCnt2 : 32; /* * [31:0]Couner 2 accroding to counter configure register. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CNT2_U;

/* **
 * Union name :    SMMC_L_CNT3
 * @brief               SMMC_L counter 3 register
 * Description:
 */
typedef union tagUnSmmcLCnt3 {
    struct tagStSmmcLCnt3 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int smmcLCnt3 : 32; /* * [31:0]Couner 3 accroding to counter configure register. */
#else
        unsigned int smmcLCnt3 : 32; /* * [31:0]Couner 3 accroding to counter configure register. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_CNT3_U;

/* **
 * Union name :    SMMC_L_BANK_QUEUE_DEPTH_CTP0
 * @brief               SMMC_L bank queue's depth register 0
 * Description:
 */
typedef union tagUnSmmcLBankQueueDepthCtp0 {
    struct tagStSmmcLBankQueueDepthCtp0 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int curDepthBank7 : 4; /* * [31:28]Current depth of bank 7 queue.Notice that depth of bank is up to 15,
                                     because only 15 threads of SMEG1 are active in normal mode, and 1 thread is
                                     reserved for de bug mode. */
        unsigned int curDepthBank6 : 4; /* * [27:24]Current depth of bank 6 queue. */
        unsigned int curDepthBank5 : 4; /* * [23:20]Current depth of bank 5 queue. */
        unsigned int curDepthBank4 : 4; /* * [19:16]Current depth of bank 4 queue. */
        unsigned int curDepthBank3 : 4; /* * [15:12]Current depth of bank 3 queue. */
        unsigned int curDepthBank2 : 4; /* * [11:8]Current depth of bank 2 queue. */
        unsigned int curDepthBank1 : 4; /* * [7:4]Current depth of bank 1 queue. */
        unsigned int curDepthBank0 : 4; /* * [3:0]Current depth of bank 0 queue. */
#else
        unsigned int curDepthBank0 : 4; /* * [3:0]Current depth of bank 0 queue. */
        unsigned int curDepthBank1 : 4; /* * [7:4]Current depth of bank 1 queue. */
        unsigned int curDepthBank2 : 4; /* * [11:8]Current depth of bank 2 queue. */
        unsigned int curDepthBank3 : 4; /* * [15:12]Current depth of bank 3 queue. */
        unsigned int curDepthBank4 : 4; /* * [19:16]Current depth of bank 4 queue. */
        unsigned int curDepthBank5 : 4; /* * [23:20]Current depth of bank 5 queue. */
        unsigned int curDepthBank6 : 4; /* * [27:24]Current depth of bank 6 queue. */
        unsigned int curDepthBank7 : 4; /* * [31:28]Current depth of bank 7 queue.Notice that depth of bank is up to 15,
                                     because only 15 threads of SMEG1 are active in normal mode, and 1 thread is
                                     reserved for de bug mode. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_U;

/* **
 * Union name :    SMMC_L_BANK_QUEUE_DEPTH_CTP1
 * @brief               SMMC_L bank queue's depth register 1
 * Description:
 */
typedef union tagUnSmmcLBankQueueDepthCtp1 {
    struct tagStSmmcLBankQueueDepthCtp1 {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int curDepthBank15 : 4; /* * [31:28]Current depth of bank 15 queue.Notice that depth of bank is up to
                                      15, because only 15 threads of SMEG1 are active in normal mode, and 1 thread is
                                      reserved for d ebug mode. */
        unsigned int curDepthBank14 : 4; /* * [27:24]Current depth of bank 14 queue. */
        unsigned int curDepthBank13 : 4; /* * [23:20]Current depth of bank 13 queue. */
        unsigned int curDepthBank12 : 4; /* * [19:16]Current depth of bank 12 queue. */
        unsigned int curDepthBank11 : 4; /* * [15:12]Current depth of bank 11 queue. */
        unsigned int curDepthBank10 : 4; /* * [11:8]Current depth of bank 10 queue. */
        unsigned int curDepthBank9 : 4;  /* * [7:4]Current depth of bank 9 queue. */
        unsigned int curDepthBank8 : 4;  /* * [3:0]Current depth of bank 8 queue. */
#else
        unsigned int curDepthBank8 : 4; /* * [3:0]Current depth of bank 8 queue. */
        unsigned int curDepthBank9 : 4; /* * [7:4]Current depth of bank 9 queue. */
        unsigned int curDepthBank10 : 4;  /* * [11:8]Current depth of bank 10 queue. */
        unsigned int curDepthBank11 : 4;  /* * [15:12]Current depth of bank 11 queue. */
        unsigned int curDepthBank12 : 4;  /* * [19:16]Current depth of bank 12 queue. */
        unsigned int curDepthBank13 : 4;  /* * [23:20]Current depth of bank 13 queue. */
        unsigned int curDepthBank14 : 4;  /* * [27:24]Current depth of bank 14 queue. */
        unsigned int curDepthBank15 : 4;  /* * [31:28]Current depth of bank 15 queue.Notice that depth of bank is up to
                                       15, because only 15 threads of SMEG1 are active in normal mode, and 1 thread is
                                       reserved for d ebug mode. */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_U;

/* **
 * Union name :    SMMC_L_ECC_INJ_CFG
 * @brief               SMMC_L ECC inject register
 * Description:
 */
typedef union tagUnSmmcLEccInjCfg {
    struct tagStSmmcLEccInjCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 30;       /* * [31:2]Reserved */
        unsigned int smmcL2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read Data memory0: disable1:
                                             enable */
        unsigned int smmcL1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read Data memory0: disable1:
                                             enable */
#else
        unsigned int smmcL1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read Data memory0: disable1:
                                             enable */
        unsigned int smmcL2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read Data memory0: disable1:
                                             enable */
        unsigned int reserved : 30;       /* * [31:2]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_ECC_INJ_CFG_U;

/* **
 * Union name :    SMMC_L_PG_CFG
 * @brief               SMMC_L Partial Good register
 * Description:
 */
typedef union tagUnSmmcLPgCfg {
    struct tagStSmmcLPgCfg {
        /* * Define the struct bits */
#if (BYTE_ORDER == BIG_ENDIAN)
        unsigned int reserved : 27;     /* * [31:5]Reserved */
        unsigned int smmcLPgGrpNum : 1; /* * [4:4]If any group has uncorrected error, SMMC_L can support 2 groups in
                                     paritial good mode.The number of bank group in paritial good mode:0: 4 groups/16
                                     banks is ena ble;1: 2 groups/8 banks is enable */
        unsigned int smmcLPgGrp0Id : 2; /* * [3:2]This field is valid only if smmc_l_pg_grp_num is configured to 2 group
                                     mode.The 1st group ID of PG.Group 0: bank 0~3Group 1: bank 4~7Group 2: bank
                                     8~11Group 3: bank 12~15.For example, if only support group 1 and group 2,
                                     pg_grp0_id must set to 1 and pg_grp1_id must set to 2.
                                      */
        unsigned int smmcLPgGrp1Id : 2; /* * [1:0]This field is valid only if smmc_l_pg_grp_num is configured to 2 group
                                     mode.The 2nd group ID of PGGroup 0: bank 0~3Group 1: bank 4~7Group 2: bank
                                     8~11Group 3: b ank 12~15 */
#else
        unsigned int smmcLPgGrp1Id : 2; /* * [1:0]This field is valid only if smmc_l_pg_grp_num is configured to 2 group
                                     mode.The 2nd group ID of PGGroup 0: bank 0~3Group 1: bank 4~7Group 2: bank
                                     8~11Group 3: b ank 12~15 */
        unsigned int smmcLPgGrp0Id : 2; /* * [3:2]This field is valid only if smmc_l_pg_grp_num is configured to 2 group
                                     mode.The 1st group ID of PG.Group 0: bank 0~3Group 1: bank 4~7Group 2: bank
                                     8~11Group 3: bank 12~15.For example, if only support group 1 and group 2,
                                     pg_grp0_id must set to 1 and pg_grp1_id must set to 2.
                                      */
        unsigned int smmcLPgGrpNum : 1; /* * [4:4]If any group has uncorrected error, SMMC_L can support 2 groups in
                                     paritial good mode.The number of bank group in paritial good mode:0: 4 groups/16
                                     banks is ena ble;1: 2 groups/8 banks is enable */
        unsigned int reserved : 27;     /* * [31:5]Reserved */
#endif
    } bs;
    /* * Define an unsigned member */
    unsigned int ulValue;
} CSR_SMMC_L_PG_CFG_U;


#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* * __cplusplus */

#endif /* * HI1823_CSR_SM_TYPEDEF_H */
